Verilog-Perl

Works for me; please send an example.

  task void_recast;
   void'( afunc(1'b1) );
  endtask

Hi Wilson,

I havent prepared an example yet, I'm tracing the problem, and it seems to be related to functions inside interfaces. Something like this:

interface my_fifo_interface (...);
   // some signals....
   ...
   // a function definition
   // this function returns a single bit
   function automatic bit try_push ( input t_data data  );
      ...
      ...
      return  ... //(1'b1 if push succeded, '0 otherwise);
   endfunction
   ...
   // A modport exporting this function
   modport push_mp ( import try_push, ...);
   ...
endinterface

// now a module that receives this interface and uses the function
module fifo_client ( my_fifo_interface i, ... );
   ...
   // some process
   always_comb begin
     ...
     void'(i.try_push(local_data));
     ...
   end
   ...
endmodule

As soon as I have a working (or failing in this case) example, I'll upload it, in the mean time this is what I have gathered about the problem.

Thanks, David

Thanks for the example, it works fine for me. Maybe you're not using the latest version?