Verilog-Perl

Hello, As discussed earleir with Wilson, found a bug in the Parser, description: when using the following code (notice the ',' after lastPort) the parser gives a syntax error:

Module my_module( portA, portB, . . . lastPort, );

the spec says: list_of_ports ::= '(' port { ',' port } ')' port ::= [ port_expression ]

So that's actually legal. However it doesn't do what you think, as it defines another port that's empty that should be connected if doing position based interconnection, so really your code should be fixed as I doubt that's ever the intent.

I think that the best way to resolve this issue is not to let it pass by, but to give a warning about it since it is definetly bad coding that might cause troubles.