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	#	Project	Tracker	Status	Priority	Subject	Assignee	Updated
	50	Verilator	Issue	Feature	Normal	Clock gating support?		10/28/2009 01:51 pm
	207	Verilator	Issue	Feature	Normal	Support assignment between packed arrays with different dimensions	Byron Bradley	01/19/2010 08:43 pm
	102	Verilator	Issue	Feature	Normal	Support "interface" and "endinterface" keywords	Byron Bradley	02/04/2010 11:16 am
	225	Verilator	Issue	Feature	Normal	hierarchical compilation of designs for scalability		03/17/2010 08:14 pm
	236	Verilator	Issue	Feature	Normal	Support real event loop		04/07/2010 01:26 pm
	235	Verilator	Issue	Feature	Normal	Support fork-joins and time delays		04/07/2010 01:27 pm
	234	Verilator	Issue	Feature	Normal	Support time and `timescales		04/07/2010 01:27 pm
	263	Dinotrace	Issue	Feature	Low	Please add support for TDML format		06/12/2010 11:19 am
	285	Verilator	Issue	Feature	Low	Verilator lint misses bogusly-typed assignment and generates invalid C++	Wilson Snyder	09/26/2010 11:15 am
	286	Verilog-mode	Issue	New	Low	Identation of classes inside package in SystemVerilog	Michael McNamara	09/27/2010 07:41 am
	63	Verilator	Issue	Feature	Normal	False Signal unoptimizable: circular logic warning		10/25/2010 08:07 pm
	279	Verilog-mode	Issue	Assigned	Normal	SystemVerilog Constraint auto-indentation	Michael McNamara	12/02/2010 02:53 pm
	320	Verilog-mode	Issue	Assigned	Normal	Interface port connection using .* is wrong (?)	Wilson Snyder	01/27/2011 09:56 pm
	324	Verilog-mode	Issue	Assigned	Normal	verilog-mode constraint indentation is not correct	Michael McNamara	02/04/2011 01:52 pm
	308	Verilog-mode	Issue	Feature	Normal	Indenting/Highlighting user defined types	Michael McNamara	02/21/2011 02:21 am
	330	Verilog-mode	Issue	New	Normal	Identation after always* construct inside named block	Michael McNamara	03/09/2011 02:59 am
	337	Verilator	Issue	Feature	Normal	Compile Issue with Large Design with Large I/O Buswidth	Wilson Snyder	03/30/2011 11:22 am
	366	Verilator	Issue	Assigned	Normal	Unsupported sensitivity of arrayed variables		07/21/2011 11:31 am
	365	Verilator	Issue	Assigned	Normal	bidrectional arrays not supported as module ports		07/21/2011 11:33 am
	380	Verilator	Issue	Feature	Normal	Support of VHDL93	Sebastien Van Cauwenberghe	08/10/2011 06:49 am
	372	Verilog-mode	Issue	Feature	Low	Feature request - add syntax highlighting to C pre-processor directives	Michael McNamara	08/25/2011 08:52 pm
	387	SystemPerl	Issue	Assigned	Normal	system perl cannot handle 2 uses of SP_TEMPLATE	Wilson Snyder	09/28/2011 11:13 am
	416	SVN::S4	Issue	New	Normal	s4 view command support for regexps at multiple levels of directory hierarchy	Wilson Snyder	11/07/2011 06:00 pm
	417	SVN::S4	Issue	New	Normal	Potential new s4 commands: doview and unview	Wilson Snyder	11/07/2011 06:13 pm
	418	SVN::S4	Issue	New	Normal	aliased entries in s4_state cause warnings on s4 update	Wilson Snyder	11/07/2011 06:41 pm
	419	SVN::S4	Issue	New	Normal	s4 update fails to remove a view when it is removed from viewspec	Wilson Snyder	11/09/2011 12:39 pm
	421	Verilator	Issue	Feature	Normal	Add an option for a custom header comment	Jeremy Bennett	11/17/2011 09:02 am
	104	Verilog-mode	Issue	Feedback	Normal	Indentation failures in v528	Michael McNamara	12/15/2011 06:50 pm
	426	Verilog-Perl	Issue	Feature	Normal	Add ability to not process some `ifdefs		12/23/2011 02:48 pm
	427	Verilog-mode	Issue	New	Normal	alignment in always @(*) blocks behaves strangely	Michael McNamara	01/02/2012 05:05 pm
	437	Verilog-mode	Issue	New	Normal	Indentation of continued assignment incorrect if first line ends with ']'		02/03/2012 02:38 pm
	386	Verilog-mode	Issue	New	Normal	Indenting of user-defined data types		02/06/2012 01:08 am
	439	Verilog-mode	Issue	Assigned	Normal	Indentation problems after `ovm_do_with macro	Wilson Snyder	02/09/2012 12:49 pm
	430	Verilog-mode	Issue	New	Normal	Incorrect indentation in Verilog Mode v736	Michael McNamara	02/23/2012 05:27 pm
	378	Verilator	Issue	Feature	Normal	Support properties and assertions		03/02/2012 11:42 pm
	377	Verilator	Issue	Feature	Normal	Support classes and methods		03/02/2012 11:42 pm
	379	Verilator	Issue	Feature	Normal	Support dynamic memory new and delete		03/02/2012 11:42 pm
	447	Verilog-mode	Issue	Assigned	Normal	verilog-pretty-expr doesn't work in latest version	Michael McNamara	03/07/2012 12:23 am
	449	Verilator	Issue	Assigned	Normal	Using public accessor tasks/functions to read and write registers causes BLKANDNBLK error	Wilson Snyder	03/07/2012 02:09 pm
	408	Verilator	Issue	Assigned	Low	verilator generates incorrect C++ code when genvar is used incorrectly		03/10/2012 07:09 am
	460	Verilator	Issue	Feature	Normal	Support enumeration type methods		03/21/2012 12:38 am
	466	Verilator	Issue	Feature	Normal	Support wires with array declarations		03/23/2012 12:51 pm
	435	Verilog-mode	Issue	New	Normal	Indenting comments on declarations in v736		03/30/2012 09:57 am
	271	Verilog-mode	Issue	New	Normal	Indentation issues with doxygen comments	Michael McNamara	03/30/2012 09:57 am
	476	Verilator	Issue	Feature	Low	Support && inside sensitivity list		04/03/2012 10:15 pm
	376	Verilator	Issue	Feature	Normal	Support "parameter type"		04/08/2012 10:02 pm
	364	Verilator	Issue	Assigned	Low	blocking & non-blocking assigns -- verilator issues error when no logical conflict exists	Wilson Snyder	04/15/2012 08:28 pm
	485	Verilator	Issue	Feature	Low	verilator does not detect if block name is used twice		04/19/2012 09:46 pm
	467	Verilator	Issue	Feature	Low	Support old format $display ($time, "...")		04/24/2012 07:21 pm
	468	Verilator	Issue	Feature	Low	Support primitive instantiations		04/25/2012 12:43 am
	493	Verilator	Issue	Feature	Low	suppress useless width warning on string parameter comparisons		04/26/2012 08:24 pm
	496	Verilator	Issue	Feature	Low	Unsupported: tristate construct: ASSIGNDLY		04/26/2012 11:14 pm
	506	Verilator	Issue	Feature	Normal	Support SystemVerilog string initializations		05/05/2012 03:39 pm
	256	Verilog-Perl	Issue	Assigned	Normal	vhier support of "myreg <= #`FFDLY 'b0;" Verilog notation	Wilson Snyder	05/07/2012 12:36 pm
	509	Verilator	Issue	Assigned	Low	Better error when illegal bit select of array		05/10/2012 07:14 am
	332	Verilog-mode	Issue	New	Normal	Calculated parameters in port widths	Wilson Snyder	05/31/2012 01:51 pm
	526	Verilog-Perl	Issue	Feature	Normal	Support UVM	Wilson Snyder	06/21/2012 01:10 pm
	385	Verilator	Issue	Feature	Low	Dpi exported tasks with array inputs don't compile.	Wilson Snyder	07/15/2012 03:19 pm
	527	Verilog-Perl	Issue	AskedReporter	High	segmentation fault in Preproc.so	Wilson Snyder	07/15/2012 03:22 pm
	533	Verilator	Issue	Assigned	Low	Missing width warning when part of a bus is compared		07/20/2012 03:27 pm
	537	Verilog-Perl	Issue	AskedReporter	Normal	Explicit hierarchical reference not resolving in Verilog::Net (CELL outside of module definition)		07/28/2012 11:22 pm
	545	Verilator	Issue	Feature	Normal	Support queues		08/09/2012 01:58 am
	546	Verilator	Issue	Assigned	Normal	Support static inside task		08/10/2012 11:42 pm
	544	Verilator	Issue	Feature	Normal	Support associative arrays		08/10/2012 11:57 pm
	355	Verilator	Issue	Feature	Normal	Support '{...}		08/12/2012 07:14 pm
	549	Verilog-mode	Issue	New	Normal	verilog-in-slash-comment-p doesn't return true	Michael McNamara	08/15/2012 01:37 am
	556	Verilog-mode	Issue	New	High	replication breaks alignment		08/27/2012 09:46 pm
	557	Verilog-mode	Issue	New	Normal	Indentation is wrong after "DPI-C" imports for context		08/31/2012 06:08 pm
	559	Verilog-mode	Issue	New	Normal	Nested ifdef with generate indentation bug	Michael McNamara	09/06/2012 09:59 pm
	560	Verilog-mode	Issue	New	Normal	Indentation following SV randomize command is incorrect		09/07/2012 02:37 pm
	517	Verilator	Issue	Feature	Normal	Constant expression in generated block index not recognized		10/08/2012 04:11 pm
	528	Verilator	Issue	Feature	Normal	Support for reserved words weak0 and weak1		11/03/2012 12:04 pm
	576	Verilator	Issue	Feature	Normal	generate/endgenerate should not be optional in Verilog 2001		11/14/2012 01:38 am
	487	Verilator	Issue	Assigned	Normal	Support short-circuiting of bitswise AND and OR	Jeremy Bennett	11/14/2012 08:06 pm
	579	Verilog-mode	Issue	New	Normal	Creating top-level ports for unsed sub-module ports.		11/15/2012 07:37 pm
	585	Verilog-mode	Patch	New	Normal	Problem with verilog-pretty-declarations function and parameter/localparam keywords, fix in attachment	Wilson Snyder	11/30/2012 01:03 pm
	336	Verilog-mode	Issue	Assigned	Normal	Incredibly slow Indenting	Michael McNamara	12/12/2012 08:20 pm
	597	Verilog-mode	Issue	Assigned	Normal	Problem with verilog-typedef-regexp	Wilson Snyder	12/31/2012 01:35 pm
	593	Verilator	Issue	Feature	Low	Support running make and creating top C file		01/15/2013 12:20 pm
	621	Verilator	Issue	Feature	Normal	Enable duplicate gate elimination in ~3.848.		02/21/2013 01:18 am
	620	Verilator	Issue	Assigned	Normal	Comparison against x and z leads to verilator crash	Wilson Snyder	02/21/2013 11:50 am
	433	Verilog-mode	Issue	New	Normal	indenting for some forms of SystemVerilog constraints is wrong/odd		02/21/2013 12:27 pm
	392	Verilator	Issue	Feature	Normal	Can't unroll generate for with complicated incrementer/init/test	Wilson Snyder	02/22/2013 10:01 pm
	622	Verilator	Issue	AskedReporter	Normal	Public signal driven by C++ not propagating as expected		02/23/2013 08:36 pm
	626	Verilog-mode	Issue	New	High	problem/question for AUTOLOGIC of array with different elements going to different instances		03/03/2013 08:13 pm
	629	Verilator	Issue	Feature	Low	Non-vector timing loop warning		03/16/2013 12:33 am
	613	Verilator	Issue	Feature	Normal	Better gated clock support		04/09/2013 02:53 pm
	636	Verilog-mode	Issue	New	Normal	SV Interface indentation issue in module ports		04/11/2013 02:12 pm
	646	Verilator	Issue	AskedReporter	Normal	Asignments of arithmetic operations embedded in a concatenation cause wrong conditional paths to be taken		05/19/2013 02:00 pm
	647	Verilog-mode	Issue	New	Normal	verilog-read-defines issue with multiline comments		05/21/2013 07:24 pm
	645	Verilator	Issue	Resolved	Normal	VL_INW and VL_OUTW macros require 4 arguments, but only 3 given	Wilson Snyder	05/21/2013 11:52 pm
	649	Verilator	Issue	Feature	Normal	support for streaming operators		05/22/2013 12:31 am
	562	Verilog-mode	Issue	Feature	Normal	bus width alignment		05/22/2013 02:11 am
	648	Verilator	Issue	Assigned	Normal	Error-BLKANDNBLK with nested modules in generate block		05/22/2013 02:41 am
	650	Verilator	Issue	New	Normal	"make test" runs out of processes		05/23/2013 02:42 pm
	651	Verilator	Issue	New	Normal	Different versions of GCC cause Verilator generated models to succeed or fail		05/23/2013 02:55 pm

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