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	#	Project	Tracker	Status	Priority	Subject	Assignee	Updated
	544	Verilator	Issue	Feature	Normal	Support associative arrays		08/10/2012 11:57 pm
	537	Verilog-Perl	Issue	AskedReporter	Normal	Explicit hierarchical reference not resolving in Verilog::Net (CELL outside of module definition)		07/28/2012 11:22 pm
	533	Verilator	Issue	Assigned	Low	Missing width warning when part of a bus is compared		07/20/2012 03:27 pm
	528	Verilator	Issue	Feature	Normal	Support for reserved words weak0 and weak1		11/03/2012 12:04 pm
	527	Verilog-Perl	Issue	AskedReporter	High	segmentation fault in Preproc.so	Wilson Snyder	07/15/2012 03:22 pm
	526	Verilog-Perl	Issue	Feature	Normal	Support UVM	Wilson Snyder	06/21/2012 01:10 pm
	517	Verilator	Issue	Feature	Normal	Constant expression in generated block index not recognized		10/08/2012 04:11 pm
	509	Verilator	Issue	Assigned	Low	Better error when illegal bit select of array		05/10/2012 07:14 am
	506	Verilator	Issue	Feature	Normal	Support SystemVerilog string initializations		05/05/2012 03:39 pm
	496	Verilator	Issue	Feature	Low	Unsupported: tristate construct: ASSIGNDLY		04/26/2012 11:14 pm
	493	Verilator	Issue	Feature	Low	suppress useless width warning on string parameter comparisons		04/26/2012 08:24 pm
	487	Verilator	Issue	Assigned	Normal	Support short-circuiting of bitswise AND and OR	Jeremy Bennett	11/14/2012 08:06 pm
	485	Verilator	Issue	Feature	Low	verilator does not detect if block name is used twice		04/19/2012 09:46 pm
	476	Verilator	Issue	Feature	Low	Support && inside sensitivity list		04/03/2012 10:15 pm
	468	Verilator	Issue	Feature	Low	Support primitive instantiations		04/25/2012 12:43 am
	467	Verilator	Issue	Feature	Low	Support old format $display ($time, "...")		04/24/2012 07:21 pm
	466	Verilator	Issue	Feature	Normal	Support wires with array declarations		03/23/2012 12:51 pm
	460	Verilator	Issue	Feature	Normal	Support enumeration type methods		03/21/2012 12:38 am
	449	Verilator	Issue	Assigned	Normal	Using public accessor tasks/functions to read and write registers causes BLKANDNBLK error	Wilson Snyder	03/07/2012 02:09 pm
	447	Verilog-mode	Issue	Assigned	Normal	verilog-pretty-expr doesn't work in latest version	Michael McNamara	03/07/2012 12:23 am
	439	Verilog-mode	Issue	Assigned	Normal	Indentation problems after `ovm_do_with macro	Wilson Snyder	02/09/2012 12:49 pm
	437	Verilog-mode	Issue	New	Normal	Indentation of continued assignment incorrect if first line ends with ']'		02/03/2012 02:38 pm
	435	Verilog-mode	Issue	New	Normal	Indenting comments on declarations in v736		03/30/2012 09:57 am
	433	Verilog-mode	Issue	New	Normal	indenting for some forms of SystemVerilog constraints is wrong/odd		02/21/2013 12:27 pm
	430	Verilog-mode	Issue	New	Normal	Incorrect indentation in Verilog Mode v736	Michael McNamara	02/23/2012 05:27 pm

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