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	#	Project	Tracker	Status	Priority	Subject	Assignee	Updated
	557	Verilog-mode	Issue	New	Normal	Indentation is wrong after "DPI-C" imports for context		08/31/2012 06:08 pm
	546	Verilator	Issue	Assigned	Normal	Support static inside task		08/10/2012 11:42 pm
	545	Verilator	Issue	Feature	Normal	Support queues		08/09/2012 01:58 am
	544	Verilator	Issue	Feature	Normal	Support associative arrays		08/10/2012 11:57 pm
	537	Verilog-Perl	Issue	AskedReporter	Normal	Explicit hierarchical reference not resolving in Verilog::Net (CELL outside of module definition)		07/28/2012 11:22 pm
	528	Verilator	Issue	Feature	Normal	Support for reserved words weak0 and weak1		11/03/2012 12:04 pm
	517	Verilator	Issue	Feature	Normal	Constant expression in generated block index not recognized		10/08/2012 04:11 pm
	506	Verilator	Issue	Feature	Normal	Support SystemVerilog string initializations		05/05/2012 03:39 pm
	466	Verilator	Issue	Feature	Normal	Support wires with array declarations		03/23/2012 12:51 pm
	460	Verilator	Issue	Feature	Normal	Support enumeration type methods		03/21/2012 12:38 am
	437	Verilog-mode	Issue	New	Normal	Indentation of continued assignment incorrect if first line ends with ']'		02/03/2012 02:38 pm
	435	Verilog-mode	Issue	New	Normal	Indenting comments on declarations in v736		03/30/2012 09:57 am
	433	Verilog-mode	Issue	New	Normal	indenting for some forms of SystemVerilog constraints is wrong/odd		02/21/2013 12:27 pm
	426	Verilog-Perl	Issue	Feature	Normal	Add ability to not process some `ifdefs		12/23/2011 02:48 pm
	386	Verilog-mode	Issue	New	Normal	Indenting of user-defined data types		02/06/2012 01:08 am
	379	Verilator	Issue	Feature	Normal	Support dynamic memory new and delete		03/02/2012 11:42 pm
	378	Verilator	Issue	Feature	Normal	Support properties and assertions		03/02/2012 11:42 pm
	377	Verilator	Issue	Feature	Normal	Support classes and methods		03/02/2012 11:42 pm
	376	Verilator	Issue	Feature	Normal	Support "parameter type"		04/08/2012 10:02 pm
	366	Verilator	Issue	Assigned	Normal	Unsupported sensitivity of arrayed variables		07/21/2011 11:31 am
	365	Verilator	Issue	Assigned	Normal	bidrectional arrays not supported as module ports		07/21/2011 11:33 am
	355	Verilator	Issue	Feature	Normal	Support '{...}		08/12/2012 07:14 pm
	236	Verilator	Issue	Feature	Normal	Support real event loop		04/07/2010 01:26 pm
	235	Verilator	Issue	Feature	Normal	Support fork-joins and time delays		04/07/2010 01:27 pm
	234	Verilator	Issue	Feature	Normal	Support time and `timescales		04/07/2010 01:27 pm

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