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	#	Project	Tracker	Status	Priority	Subject	Assignee	Updated
	421	Verilator	Issue	Feature	Normal	Add an option for a custom header comment	Jeremy Bennett	11/17/2011 09:02 am
	104	Verilog-mode	Issue	Feedback	Normal	Indentation failures in v528	Michael McNamara	12/15/2011 06:50 pm
	426	Verilog-Perl	Issue	Feature	Normal	Add ability to not process some `ifdefs		12/23/2011 02:48 pm
	427	Verilog-mode	Issue	New	Normal	alignment in always @(*) blocks behaves strangely	Michael McNamara	01/02/2012 05:05 pm
	437	Verilog-mode	Issue	New	Normal	Indentation of continued assignment incorrect if first line ends with ']'		02/03/2012 02:38 pm
	386	Verilog-mode	Issue	New	Normal	Indenting of user-defined data types		02/06/2012 01:08 am
	439	Verilog-mode	Issue	Assigned	Normal	Indentation problems after `ovm_do_with macro	Wilson Snyder	02/09/2012 12:49 pm
	430	Verilog-mode	Issue	New	Normal	Incorrect indentation in Verilog Mode v736	Michael McNamara	02/23/2012 05:27 pm
	378	Verilator	Issue	Feature	Normal	Support properties and assertions		03/02/2012 11:42 pm
	377	Verilator	Issue	Feature	Normal	Support classes and methods		03/02/2012 11:42 pm
	379	Verilator	Issue	Feature	Normal	Support dynamic memory new and delete		03/02/2012 11:42 pm
	447	Verilog-mode	Issue	Assigned	Normal	verilog-pretty-expr doesn't work in latest version	Michael McNamara	03/07/2012 12:23 am
	449	Verilator	Issue	Assigned	Normal	Using public accessor tasks/functions to read and write registers causes BLKANDNBLK error	Wilson Snyder	03/07/2012 02:09 pm
	460	Verilator	Issue	Feature	Normal	Support enumeration type methods		03/21/2012 12:38 am
	466	Verilator	Issue	Feature	Normal	Support wires with array declarations		03/23/2012 12:51 pm
	435	Verilog-mode	Issue	New	Normal	Indenting comments on declarations in v736		03/30/2012 09:57 am
	271	Verilog-mode	Issue	New	Normal	Indentation issues with doxygen comments	Michael McNamara	03/30/2012 09:57 am
	376	Verilator	Issue	Feature	Normal	Support "parameter type"		04/08/2012 10:02 pm
	506	Verilator	Issue	Feature	Normal	Support SystemVerilog string initializations		05/05/2012 03:39 pm
	256	Verilog-Perl	Issue	Assigned	Normal	vhier support of "myreg <= #`FFDLY 'b0;" Verilog notation	Wilson Snyder	05/07/2012 12:36 pm
	332	Verilog-mode	Issue	New	Normal	Calculated parameters in port widths	Wilson Snyder	05/31/2012 01:51 pm
	526	Verilog-Perl	Issue	Feature	Normal	Support UVM	Wilson Snyder	06/21/2012 01:10 pm
	537	Verilog-Perl	Issue	AskedReporter	Normal	Explicit hierarchical reference not resolving in Verilog::Net (CELL outside of module definition)		07/28/2012 11:22 pm
	545	Verilator	Issue	Feature	Normal	Support queues		08/09/2012 01:58 am
	546	Verilator	Issue	Assigned	Normal	Support static inside task		08/10/2012 11:42 pm

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