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	#	Project	Tracker	Status	Priority	Subject	Assignee	Updated
	517	Verilator	Issue	Feature	Normal	Constant expression in generated block index not recognized		10/08/2012 04:11 pm
	528	Verilator	Issue	Feature	Normal	Support for reserved words weak0 and weak1		11/03/2012 12:04 pm
	544	Verilator	Issue	Feature	Normal	Support associative arrays		08/10/2012 11:57 pm
	545	Verilator	Issue	Feature	Normal	Support queues		08/09/2012 01:58 am
	576	Verilator	Issue	Feature	Normal	generate/endgenerate should not be optional in Verilog 2001		11/14/2012 01:38 am
	613	Verilator	Issue	Feature	Normal	Better gated clock support		04/09/2013 02:53 pm
	621	Verilator	Issue	Feature	Normal	Enable duplicate gate elimination in ~3.848.		02/21/2013 01:18 am
	102	Verilator	Issue	Feature	Normal	Support "interface" and "endinterface" keywords	Byron Bradley	02/04/2010 11:16 am
	207	Verilator	Issue	Feature	Normal	Support assignment between packed arrays with different dimensions	Byron Bradley	01/19/2010 08:43 pm
	487	Verilator	Issue	Assigned	Normal	Support short-circuiting of bitswise AND and OR	Jeremy Bennett	11/14/2012 08:06 pm
	421	Verilator	Issue	Feature	Normal	Add an option for a custom header comment	Jeremy Bennett	11/17/2011 09:02 am
	380	Verilator	Issue	Feature	Normal	Support of VHDL93	Sebastien Van Cauwenberghe	08/10/2011 06:49 am
	449	Verilator	Issue	Assigned	Normal	Using public accessor tasks/functions to read and write registers causes BLKANDNBLK error	Wilson Snyder	03/07/2012 02:09 pm
	620	Verilator	Issue	Assigned	Normal	Comparison against x and z leads to verilator crash	Wilson Snyder	02/21/2013 11:50 am
	645	Verilator	Issue	AskedReporter	Normal	VL_INW and VL_OUTW macros require 4 arguments, but only 3 given	Wilson Snyder	05/19/2013 12:18 am
	337	Verilator	Issue	Feature	Normal	Compile Issue with Large Design with Large I/O Buswidth	Wilson Snyder	03/30/2011 11:22 am
	392	Verilator	Issue	Feature	Normal	Can't unroll generate for with complicated incrementer/init/test	Wilson Snyder	02/22/2013 10:01 pm
	408	Verilator	Issue	Assigned	Low	verilator generates incorrect C++ code when genvar is used incorrectly		03/10/2012 07:09 am
	509	Verilator	Issue	Assigned	Low	Better error when illegal bit select of array		05/10/2012 07:14 am
	533	Verilator	Issue	Assigned	Low	Missing width warning when part of a bus is compared		07/20/2012 03:27 pm
	467	Verilator	Issue	Feature	Low	Support old format $display ($time, "...")		04/24/2012 07:21 pm
	468	Verilator	Issue	Feature	Low	Support primitive instantiations		04/25/2012 12:43 am
	476	Verilator	Issue	Feature	Low	Support && inside sensitivity list		04/03/2012 10:15 pm
	485	Verilator	Issue	Feature	Low	verilator does not detect if block name is used twice		04/19/2012 09:46 pm
	493	Verilator	Issue	Feature	Low	suppress useless width warning on string parameter comparisons		04/26/2012 08:24 pm

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