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	#	Project	Tracker	Status	Priority	Subject	Assignee	Updated
	557	Verilog-mode	Issue	New	Normal	Indentation is wrong after "DPI-C" imports for context		08/31/2012 06:08 pm
	556	Verilog-mode	Issue	New	High	replication breaks alignment		08/27/2012 09:46 pm
	549	Verilog-mode	Issue	New	Normal	verilog-in-slash-comment-p doesn't return true	Michael McNamara	08/15/2012 01:37 am
	355	Verilator	Issue	Feature	Normal	Support '{...}		08/12/2012 07:14 pm
	544	Verilator	Issue	Feature	Normal	Support associative arrays		08/10/2012 11:57 pm
	546	Verilator	Issue	Assigned	Normal	Support static inside task		08/10/2012 11:42 pm
	545	Verilator	Issue	Feature	Normal	Support queues		08/09/2012 01:58 am
	537	Verilog-Perl	Issue	AskedReporter	Normal	Explicit hierarchical reference not resolving in Verilog::Net (CELL outside of module definition)		07/28/2012 11:22 pm
	533	Verilator	Issue	Assigned	Low	Missing width warning when part of a bus is compared		07/20/2012 03:27 pm
	527	Verilog-Perl	Issue	AskedReporter	High	segmentation fault in Preproc.so	Wilson Snyder	07/15/2012 03:22 pm
	385	Verilator	Issue	Feature	Low	Dpi exported tasks with array inputs don't compile.	Wilson Snyder	07/15/2012 03:19 pm
	526	Verilog-Perl	Issue	Feature	Normal	Support UVM	Wilson Snyder	06/21/2012 01:10 pm
	332	Verilog-mode	Issue	New	Normal	Calculated parameters in port widths	Wilson Snyder	05/31/2012 01:51 pm
	509	Verilator	Issue	Assigned	Low	Better error when illegal bit select of array		05/10/2012 07:14 am
	256	Verilog-Perl	Issue	Assigned	Normal	vhier support of "myreg <= #`FFDLY 'b0;" Verilog notation	Wilson Snyder	05/07/2012 12:36 pm
	506	Verilator	Issue	Feature	Normal	Support SystemVerilog string initializations		05/05/2012 03:39 pm
	496	Verilator	Issue	Feature	Low	Unsupported: tristate construct: ASSIGNDLY		04/26/2012 11:14 pm
	493	Verilator	Issue	Feature	Low	suppress useless width warning on string parameter comparisons		04/26/2012 08:24 pm
	468	Verilator	Issue	Feature	Low	Support primitive instantiations		04/25/2012 12:43 am
	467	Verilator	Issue	Feature	Low	Support old format $display ($time, "...")		04/24/2012 07:21 pm
	485	Verilator	Issue	Feature	Low	verilator does not detect if block name is used twice		04/19/2012 09:46 pm
	364	Verilator	Issue	Assigned	Low	blocking & non-blocking assigns -- verilator issues error when no logical conflict exists	Wilson Snyder	04/15/2012 08:28 pm
	376	Verilator	Issue	Feature	Normal	Support "parameter type"		04/08/2012 10:02 pm
	476	Verilator	Issue	Feature	Low	Support && inside sensitivity list		04/03/2012 10:15 pm
	271	Verilog-mode	Issue	New	Normal	Indentation issues with doxygen comments	Michael McNamara	03/30/2012 09:57 am

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