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Status Filter open is is not closed all New Feature AskedReporter Assigned Resolved Feedback Closed WillNotFix NoFixNeeded NotEnoughInfo Duplicate Project Filter is is not BugVise CovVise Dinotrace Force-Gate-Sim Gspice IPC::Locker Metrigator Rsvn Schedule::Load SVN::S4 Synopsys-Modes SystemPerl TestProject Verilator Verilog-mode Verilog-Perl Verilog-Pli Veripool Voneline Vregs WFH Tracker Filter is is not Issue Patch Priority Filter is is not Low Normal High Urgent Assignee Filter is is not none all Auto Update Daemon Bobby Woods-Corwin Byron Bradley Duane Galbi Jeremy Bennett Lane Brooks Michael McNamara Sebastien Van Cauwenberghe Wilson Snyder Author Filter is is not Auto Update Daemon Bobby Woods-Corwin Byron Bradley Duane Galbi Jeremy Bennett Lane Brooks Michael McNamara Sebastien Van Cauwenberghe Wilson Snyder Assignee's role Filter is is not none all Manager Developer Member Subject Filter contains doesn't contain Created Filter is >= <= between less than days ago more than days ago days ago today this week none all days Updated Filter is >= <= between less than days ago more than days ago days ago today this week none all days Start date Filter is >= <= between in less than in more than in today this week less than days ago more than days ago days ago none all days Due date Filter is >= <= between in less than in more than in today this week less than days ago more than days ago days ago none all days Estimated time Filter is >= <= between none all % Done Filter is >= <= between none all

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	#	Project	Tracker	Status	Priority	Subject	Assignee	Updated
	256	Verilog-Perl	Issue	Assigned	Normal	vhier support of "myreg <= #`FFDLY 'b0;" Verilog notation	Wilson Snyder	05/07/2012 12:36 pm
	629	Verilator	Issue	Feature	Low	Non-vector timing loop warning		03/16/2013 12:33 am
	593	Verilator	Issue	Feature	Low	Support running make and creating top C file		01/15/2013 12:20 pm
	533	Verilator	Issue	Assigned	Low	Missing width warning when part of a bus is compared		07/20/2012 03:27 pm
	509	Verilator	Issue	Assigned	Low	Better error when illegal bit select of array		05/10/2012 07:14 am
	496	Verilator	Issue	Feature	Low	Unsupported: tristate construct: ASSIGNDLY		04/26/2012 11:14 pm
	493	Verilator	Issue	Feature	Low	suppress useless width warning on string parameter comparisons		04/26/2012 08:24 pm
	485	Verilator	Issue	Feature	Low	verilator does not detect if block name is used twice		04/19/2012 09:46 pm
	476	Verilator	Issue	Feature	Low	Support && inside sensitivity list		04/03/2012 10:15 pm
	468	Verilator	Issue	Feature	Low	Support primitive instantiations		04/25/2012 12:43 am
	467	Verilator	Issue	Feature	Low	Support old format $display ($time, "...")		04/24/2012 07:21 pm
	408	Verilator	Issue	Assigned	Low	verilator generates incorrect C++ code when genvar is used incorrectly		03/10/2012 07:09 am
	263	Dinotrace	Issue	Feature	Low	Please add support for TDML format		06/12/2010 11:19 am
	372	Verilog-mode	Issue	Feature	Low	Feature request - add syntax highlighting to C pre-processor directives	Michael McNamara	08/25/2011 08:52 pm
	286	Verilog-mode	Issue	New	Low	Identation of classes inside package in SystemVerilog	Michael McNamara	09/27/2010 07:41 am
	385	Verilator	Issue	Feature	Low	Dpi exported tasks with array inputs don't compile.	Wilson Snyder	07/15/2012 03:19 pm
	364	Verilator	Issue	Assigned	Low	blocking & non-blocking assigns -- verilator issues error when no logical conflict exists	Wilson Snyder	04/15/2012 08:28 pm
	285	Verilator	Issue	Feature	Low	Verilator lint misses bogusly-typed assignment and generates invalid C++	Wilson Snyder	09/26/2010 11:15 am

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