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Issues

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Toggle_check # Project Tracker Status Priority Subject Assignee Updated
649 VerilatorIssueFeatureNormalsupport for streaming operators05/22/2013 12:31 am
648 VerilatorIssueAssignedNormalError-BLKANDNBLK with nested modules in generate block05/22/2013 02:41 am
647 Verilog-modeIssueNewNormalverilog-read-defines issue with multiline comments05/21/2013 07:24 pm
646 VerilatorIssueAskedReporterNormalAsignments of arithmetic operations embedded in a concatenation cause wrong conditional paths to be taken05/19/2013 02:00 pm
645 VerilatorIssueResolvedNormalVL_INW and VL_OUTW macros require 4 arguments, but only 3 givenWilson Snyder05/21/2013 11:52 pm
636 Verilog-modeIssueNewNormalSV Interface indentation issue in module ports04/11/2013 02:12 pm
629 VerilatorIssueFeatureLowNon-vector timing loop warning03/16/2013 12:33 am
626 Verilog-modeIssueNewHighproblem/question for AUTOLOGIC of array with different elements going to different instances03/03/2013 08:13 pm
622 VerilatorIssueAskedReporterNormalPublic signal driven by C++ not propagating as expected02/23/2013 08:36 pm
621 VerilatorIssueFeatureNormalEnable duplicate gate elimination in ~3.848.02/21/2013 01:18 am
620 VerilatorIssueAssignedNormalComparison against x and z leads to verilator crashWilson Snyder02/21/2013 11:50 am
613 VerilatorIssueFeatureNormalBetter gated clock support04/09/2013 02:53 pm
597 Verilog-modeIssueAssignedNormalProblem with verilog-typedef-regexpWilson Snyder12/31/2012 01:35 pm
593 VerilatorIssueFeatureLowSupport running make and creating top C file01/15/2013 12:20 pm
585 Verilog-modePatchNewNormalProblem with verilog-pretty-declarations function and parameter/localparam keywords, fix in attachmentWilson Snyder11/30/2012 01:03 pm
579 Verilog-modeIssueNewNormalCreating top-level ports for unsed sub-module ports.11/15/2012 07:37 pm
576 VerilatorIssueFeatureNormalgenerate/endgenerate should not be optional in Verilog 200111/14/2012 01:38 am
562 Verilog-modeIssueFeatureNormalbus width alignment05/22/2013 02:11 am
560 Verilog-modeIssueNewNormalIndentation following SV randomize command is incorrect09/07/2012 02:37 pm
559 Verilog-modeIssueNewNormalNested ifdef with generate indentation bugMichael McNamara09/06/2012 09:59 pm
557 Verilog-modeIssueNewNormalIndentation is wrong after "DPI-C" imports for context08/31/2012 06:08 pm
556 Verilog-modeIssueNewHighreplication breaks alignment08/27/2012 09:46 pm
549 Verilog-modeIssueNewNormalverilog-in-slash-comment-p doesn't return trueMichael McNamara08/15/2012 01:37 am
546 VerilatorIssueAssignedNormalSupport static inside task08/10/2012 11:42 pm
545 VerilatorIssueFeatureNormalSupport queues08/09/2012 01:58 am

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