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	#	Project	Tracker	Status	Priority	Subject	Assignee	Updated
	649	Verilator	Issue	Feature	Normal	support for streaming operators		05/22/2013 12:31 am
	648	Verilator	Issue	Assigned	Normal	Error-BLKANDNBLK with nested modules in generate block		05/22/2013 02:41 am
	647	Verilog-mode	Issue	New	Normal	verilog-read-defines issue with multiline comments		05/21/2013 07:24 pm
	646	Verilator	Issue	AskedReporter	Normal	Asignments of arithmetic operations embedded in a concatenation cause wrong conditional paths to be taken		05/19/2013 02:00 pm
	645	Verilator	Issue	Resolved	Normal	VL_INW and VL_OUTW macros require 4 arguments, but only 3 given	Wilson Snyder	05/21/2013 11:52 pm
	636	Verilog-mode	Issue	New	Normal	SV Interface indentation issue in module ports		04/11/2013 02:12 pm
	629	Verilator	Issue	Feature	Low	Non-vector timing loop warning		03/16/2013 12:33 am
	626	Verilog-mode	Issue	New	High	problem/question for AUTOLOGIC of array with different elements going to different instances		03/03/2013 08:13 pm
	622	Verilator	Issue	AskedReporter	Normal	Public signal driven by C++ not propagating as expected		02/23/2013 08:36 pm
	621	Verilator	Issue	Feature	Normal	Enable duplicate gate elimination in ~3.848.		02/21/2013 01:18 am
	620	Verilator	Issue	Assigned	Normal	Comparison against x and z leads to verilator crash	Wilson Snyder	02/21/2013 11:50 am
	613	Verilator	Issue	Feature	Normal	Better gated clock support		04/09/2013 02:53 pm
	597	Verilog-mode	Issue	Assigned	Normal	Problem with verilog-typedef-regexp	Wilson Snyder	12/31/2012 01:35 pm
	593	Verilator	Issue	Feature	Low	Support running make and creating top C file		01/15/2013 12:20 pm
	585	Verilog-mode	Patch	New	Normal	Problem with verilog-pretty-declarations function and parameter/localparam keywords, fix in attachment	Wilson Snyder	11/30/2012 01:03 pm
	579	Verilog-mode	Issue	New	Normal	Creating top-level ports for unsed sub-module ports.		11/15/2012 07:37 pm
	576	Verilator	Issue	Feature	Normal	generate/endgenerate should not be optional in Verilog 2001		11/14/2012 01:38 am
	562	Verilog-mode	Issue	Feature	Normal	bus width alignment		05/22/2013 02:11 am
	560	Verilog-mode	Issue	New	Normal	Indentation following SV randomize command is incorrect		09/07/2012 02:37 pm
	559	Verilog-mode	Issue	New	Normal	Nested ifdef with generate indentation bug	Michael McNamara	09/06/2012 09:59 pm
	557	Verilog-mode	Issue	New	Normal	Indentation is wrong after "DPI-C" imports for context		08/31/2012 06:08 pm
	556	Verilog-mode	Issue	New	High	replication breaks alignment		08/27/2012 09:46 pm
	549	Verilog-mode	Issue	New	Normal	verilog-in-slash-comment-p doesn't return true	Michael McNamara	08/15/2012 01:37 am
	546	Verilator	Issue	Assigned	Normal	Support static inside task		08/10/2012 11:42 pm
	545	Verilator	Issue	Feature	Normal	Support queues		08/09/2012 01:58 am

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