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	#	Project	Tracker	Status	Priority	Subject	Assignee	Updated
	426	Verilog-Perl	Issue	Feature	Normal	Add ability to not process some `ifdefs		12/23/2011 02:48 pm
	421	Verilator	Issue	Feature	Normal	Add an option for a custom header comment	Jeremy Bennett	11/17/2011 09:02 am
	418	SVN::S4	Issue	New	Normal	aliased entries in s4_state cause warnings on s4 update	Wilson Snyder	11/07/2011 06:41 pm
	427	Verilog-mode	Issue	New	Normal	alignment in always @(*) blocks behaves strangely	Michael McNamara	01/02/2012 05:05 pm
	646	Verilator	Issue	AskedReporter	Normal	Asignments of arithmetic operations embedded in a concatenation cause wrong conditional paths to be taken		05/19/2013 02:00 pm
	509	Verilator	Issue	Assigned	Low	Better error when illegal bit select of array		05/10/2012 07:14 am
	613	Verilator	Issue	Feature	Normal	Better gated clock support		04/09/2013 02:53 pm
	365	Verilator	Issue	Assigned	Normal	bidrectional arrays not supported as module ports		07/21/2011 11:33 am
	364	Verilator	Issue	Assigned	Low	blocking & non-blocking assigns -- verilator issues error when no logical conflict exists	Wilson Snyder	04/15/2012 08:28 pm
	562	Verilog-mode	Issue	Feature	Normal	bus width alignment		05/22/2013 02:11 am
	332	Verilog-mode	Issue	New	Normal	Calculated parameters in port widths	Wilson Snyder	05/31/2012 01:51 pm
	392	Verilator	Issue	Feature	Normal	Can't unroll generate for with complicated incrementer/init/test	Wilson Snyder	02/22/2013 10:01 pm
	50	Verilator	Issue	Feature	Normal	Clock gating support?		10/28/2009 01:51 pm
	620	Verilator	Issue	Assigned	Normal	Comparison against x and z leads to verilator crash	Wilson Snyder	02/21/2013 11:50 am
	337	Verilator	Issue	Feature	Normal	Compile Issue with Large Design with Large I/O Buswidth	Wilson Snyder	03/30/2011 11:22 am
	517	Verilator	Issue	Feature	Normal	Constant expression in generated block index not recognized		10/08/2012 04:11 pm
	579	Verilog-mode	Issue	New	Normal	Creating top-level ports for unsed sub-module ports.		11/15/2012 07:37 pm
	651	Verilator	Issue	Resolved	Normal	Different versions of GCC cause Verilator generated models to succeed or fail	Jeremy Bennett	05/24/2013 12:21 am
	385	Verilator	Issue	Feature	Low	Dpi exported tasks with array inputs don't compile.	Wilson Snyder	07/15/2012 03:19 pm
	621	Verilator	Issue	Feature	Normal	Enable duplicate gate elimination in ~3.848.		02/21/2013 01:18 am
	648	Verilator	Issue	Assigned	Normal	Error-BLKANDNBLK with nested modules in generate block		05/22/2013 02:41 am
	537	Verilog-Perl	Issue	AskedReporter	Normal	Explicit hierarchical reference not resolving in Verilog::Net (CELL outside of module definition)		07/28/2012 11:22 pm
	63	Verilator	Issue	Feature	Normal	False Signal unoptimizable: circular logic warning		10/25/2010 08:07 pm
	372	Verilog-mode	Issue	Feature	Low	Feature request - add syntax highlighting to C pre-processor directives	Michael McNamara	08/25/2011 08:52 pm
	576	Verilator	Issue	Feature	Normal	generate/endgenerate should not be optional in Verilog 2001		11/14/2012 01:38 am

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