Verilog-Perl

Verilog::Language 3.220 2009/09/30

• Add parsing of "assign", including SigParser::contassign callback, Netlist::ContAssign object, and related accessors.

• Several code speedups to vhier, Verilog::Netlist, and the parsers.

• Add Preproc::getall to fetch all text instead of line-by-line.

• Add Parser::new(use_cb_{name}=>0) option to speed parsing.

• Add SigParser/Netlist::new(use_vars=>0) option to speed parsing.

• Fix deep defines causing flex scanner overflows. [Brad Dobbie]

• Fix preprocessing commas in deep parameterized macros. [Brad Dobbie]

• Fix Preproc::defSubstitute not being called on parameterized macros.

• Fix Perl 5.8.8 compile error, bug115. [Marek Rouchal]