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Verilog-Perl 3.222 Released

Added by Wilson Snyder over 3 years ago

Verilog::Language 3.222 2009/11/24

  • Fix missing ; in ContAssign::verilog_text, bug177. [Nicolas Wilhelm]
  • Fix multi-dimensional arrayed typedefs, bug183. [Vesselin Kavalov]
  • Fix "assert () else" action_blocks. [Vesselin Kavalov]
  • Fix typedef scoping under anonymous begin blocks.
  • Fix `define argument mis-replacing system task of same name, bug191.

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