Verilator

Verilator 3.720 2009/10/26

• Support little endian bit vectors ("reg [0:2] x;").

• Support division and modulus of > 64 bit vectors. [Gary Thomas]

• Fix writing to out-of-bounds arrays writing element 0.

• Fix core dump with SystemVerilog var declarations under unnamed begins.

• Fix VCD files showing internal flattened hierarchy, broke in 3.714.

• Fix cell port connection to unsized integer causing false width warning.

• Fix erroring on strings with backslashed newlines, bug168. [Pete Nixon]