Verilator

Today

02:34 pm Issue #658: SystemVerilog interfaces: Internal error when connecting interfaces

I've replicated our example almost exactly now (file attached), but Verilator is happy with it (cannot recreate inter... Ed Lander

01:58 pm Issue #658: SystemVerilog interfaces: Internal error when connecting interfaces

Example updated (now with two instances of an interface propagating down through two levels of hierarchy). Clean outp... Ed Lander

01:13 pm Issue #658: SystemVerilog interfaces: Internal error when connecting interfaces

Clean example attached (to be made more complex). Ed Lander

11:45 am Issue #658: SystemVerilog interfaces: Internal error when connecting interfaces

Typo in example corrected. Ed Lander

11:17 am Issue #658: SystemVerilog interfaces: Internal error when connecting interfaces

Revised example attached. Internal error not repeated; i'll try recoding our complex example ... Ed Lander

06/18/2013

07:01 pm Issue #657: Read Parmetarized Verilog File

See the BUGS section in the end of the manual for how to create a test.
[http://www.veripool.org/projects/verilato... Joe Eiler

04:36 pm Issue #657: Read Parmetarized Verilog File

Would you please tell me where in the Document? I can not find it!
Thanks Amir Yazdanbakhsh

04:36 pm Issue #657: Read Parmetarized Verilog File

This is an incomplete example - please provide a complete example that has been checked on another simulator, see the... Wilson Snyder

04:22 pm Issue #657 (New): Read Parmetarized Verilog File

Hi,
I was trying to read a parameterized Verilog file with Verilator. But it seems it generates and error.
Attach... Amir Yazdanbakhsh

04:37 pm Issue #658: SystemVerilog interfaces: Internal error when connecting interfaces

Important clarification: whilst we define multiple / nested interfaces, our design isn't actually using the nested st... Ed Lander

04:30 pm Issue #658 (New): SystemVerilog interfaces: Internal error when connecting interfaces

Hi,
We are seeing an internal error when connecting SystemVerilog interfaces. Verilator happily compiles the inter... Ed Lander

06/17/2013

08:29 pm Issue #655: vpi memory iterator

I had just made t_vpI_var match the return values, assuming your fixes were ok. If that's not right a fix would be a... Wilson Snyder

07:57 pm Issue #655: vpi memory iterator

Oooops. Didn't mean to repost that last comment. Sorry.
But while I'm here I'll point out that the t_vpi_var issue... Rich Porter

07:51 pm Issue #655: vpi memory iterator

I've ported the t_vpi_memory test to iverilog, and it passes for both verilator and iverilog which increases my confi... Rich Porter

06/13/2013

12:06 pm Issue #655 (Resolved): vpi memory iterator

Pushed to git towards 3.851. Thanks again for patching!
Wilson Snyder

11:06 am Issue #655: vpi memory iterator

Great, I'll merge your changes then do the other name cleanup.
Wilson Snyder

10:12 am Issue #655: vpi memory iterator

I've ported the t_vpi_memory test to iverilog, and it passes for both verilator and iverilog which increases my confi... Rich Porter

06/12/2013

08:10 pm Issue #655: vpi memory iterator

I've added a test case to the branch - test_regress/t_vpi_memory, the other test case I mentioned previously was just... Rich Porter

06/06/2013

10:29 pm Issue #655: vpi memory iterator

The bug seems reasonable. The test case wasn't in your branch though so I couldn't test it to make sure.
I'm not ... Wilson Snyder

03:38 am Issue #613 (Resolved): Better gated clock support

Pushed to git towards 3.851.
Gave this a good tryout, seems stable. Good job debugging this; it's quite impressiv... Wilson Snyder

06/05/2013

01:16 pm Issue #655 (Resolved): vpi memory iterator

I think that the iterator returned by vpi_iterate with a type of vpiMemoryWord is incorrect. The diagram in IEEE 1364... Rich Porter

06/03/2013

11:08 pm Issue #654 (Closed): VCD handling regression test failure

Passed on my system, but valgrind suggested the problem.
Fixed in git towards 3.851.
Wilson Snyder

06:04 pm Issue #654 (Closed): VCD handling regression test failure

The t_trace_cat_renew fails with the current git master (commit ID 7a65df763645ece622ef7ae43b5298a902bdb3fd). It seem... Jeremy Bennett

05:40 pm Issue #613: Better gated clock support

Having worked with Jie on this, I believe it seems the problem is caused by the extra loop added for internally gener... Jeremy Bennett

06/02/2013

06:55 pm Issue #645 (Closed): VL_INW and VL_OUTW macros require 4 arguments, but only 3 given

In 3.850.
Wilson Snyder

06:54 pm Issue #652 (Closed): Width mismatch problem

In 3.850.
Wilson Snyder

06:54 pm Issue #651 (Closed): Different versions of GCC cause Verilator generated models to succeed or fail

In 3.850.
Wilson Snyder

06:54 pm Issue #621 (Closed): Enable duplicate gate elimination in ~3.848.

In 3.850.
Wilson Snyder

06:54 pm Issue #102 (Closed): Support "interface" and "endinterface" keywords

In 3.850.
Wilson Snyder

06:52 pm Verilator 3.850 Released

Verilator 3.850 2013-06-02
** Support interfaces and modports, bug102. [Byron Bradley, Jeremy Bennett]
*** ... Wilson Snyder

05/30/2013

09:57 pm Issue #653 (Assigned): vcddiff tests fail with latest gpl-cver vcddiff

Comment out for now. I know the vcddiff author and asked if he or I can make a new release.
Wilson Snyder

07:45 pm Issue #653 (Assigned): vcddiff tests fail with latest gpl-cver vcddiff

I found regression tests failing with the latest version of _vcddiff_. The problem is due to it putting out a welcome... Jeremy Bennett

05/28/2013

02:39 am Issue #621 (Resolved): Enable duplicate gate elimination in ~3.848.

Enabled in git towards 3.848.
Wilson Snyder

01:41 am Issue #102 (Resolved): Support "interface" and "endinterface" keywords

Interface support added to git towards 3.848.
Interfaces and modports, including with generated data types are sup... Wilson Snyder

05/25/2013

01:30 am Issue #652 (Resolved): Width mismatch problem

While the width warning was as noted above and remains, the crash was not a direct result of the '0. Anyhow,
Fixe... Wilson Snyder

05/24/2013

11:08 am Issue #652 (Assigned): Width mismatch problem

'0 is unsized, and IEEE says clearly 'Unsized constant numbers shall not be used in concatenations." I will fix the ... Wilson Snyder

05:06 am Issue #652 (Closed): Width mismatch problem

... Krzysztof Jankowski

12:20 am Issue #651 (Resolved): Different versions of GCC cause Verilator generated models to succeed or fail

Thanks for the patch, makes sense.
Fixed in git towards 3.848.
Wilson Snyder

12:09 am Issue #650 (Closed): "make test" runs out of processes

Fixed it to not use tee at all.
Fixed in git towards 3.848.
Wilson Snyder

05/23/2013

02:55 pm Issue #651 (Closed): Different versions of GCC cause Verilator generated models to succeed or fail

We've recently run into a design where the choice of GCC version when building Verilator, causes different behavior i... Jeremy Bennett

02:42 pm Issue #650 (Closed): "make test" runs out of processes

I recently ran out of processes on my system (64-bit Fedora 18) while running "make test". Quick inspection showed a ... Jeremy Bennett

05/22/2013

02:41 am Issue #648 (Assigned): Error-BLKANDNBLK with nested modules in generate block

I'm not immediately sure how to fix this. The conflict is at that port since a single bit is selected that is effect... Wilson Snyder

12:31 am Issue #649 (Feature): support for streaming operators

I don't personally have a huge interest in this as it's uncommon syntax, but if you or someone else would like to tak... Wilson Snyder

05/21/2013

11:58 pm Issue #649 (Feature): support for streaming operators

This is more a feature request rather than bug. Today SV's {<<{...}} and {>>{...}} operators generate syntax error, s... Krzysztof Jankowski

11:52 pm Issue #645 (Resolved): VL_INW and VL_OUTW macros require 4 arguments, but only 3 given

Wilson Snyder

11:50 pm Issue #645: VL_INW and VL_OUTW macros require 4 arguments, but only 3 given

It seems to be working now. Thanks for the quick fix! Krzysztof Jankowski

11:48 pm Issue #648 (Assigned): Error-BLKANDNBLK with nested modules in generate block

The attached code gives error: ??%Error-BLKANDNBLK: condgen.sv:29: Unsupported: Blocked and non-blocking assignments ... Krzysztof Jankowski