Verilator

05/13/2011

11:12 am Issue #349: logical shift of signed values

Sorry, I oversimplified my testcase. Take a look at this.... Thomas Watts

05/12/2011

05:18 pm Issue #350 (WillNotFix): Width mismatch warnings

True enough.
By the verilog rules, the expression "32 - 1" has width 32, which is what verilator correctly reports... Wilson Snyder

05:10 pm Issue #350 (WillNotFix): Width mismatch warnings

It seems that when assigning constant expressions to a signal, Verilator expects the LSH to be as wide as the widest ... Amin Firoozshahian

04:56 pm Issue #349 (AskedReporter): logical shift of signed values

The following code shows identical results on Verilator and several other simulators. If you can show how to give di... Wilson Snyder

02:40 pm Issue #349 (Closed): logical shift of signed values

With the following code... Thomas Watts

11:35 am Issue #347 (Resolved): DPI problem with vector task arguments

Your patch was close; it only needed to be done on bit vector types not non-vector types.
Fixed in git for 3.813.
Wilson Snyder

10:59 am Issue #346: Undeclared svBitVecVal

Looking at bug347, I needed an include in the interface too. I pushed this to git.
Wilson Snyder

10:33 am Issue #346 (Resolved): Undeclared svBitVecVal

Thanks for a great patch, looks right on.
Fixed in git for 3.813. Wilson Snyder

10:30 am Issue #341: Verilator signal value evaluation problem?

Because one simulator doesn't have races doesn't mean another won't.
Also, Verilator does not promise to follow the ... Wilson Snyder

05/10/2011

08:40 pm Issue #347: DPI problem with vector task arguments

Attached is the example and a patch that fixes the problem Chandan Egbert

08:35 pm Issue #347 (Closed): DPI problem with vector task arguments

Verilator version: Verilator 3.812 2011/04/06 rev verilator_3_811-18-ga20b4f2
When a task with vector input argume... Chandan Egbert

07:35 pm Issue #346: Undeclared svBitVecVal

The attached patch fixes the problem. The changes are in the following files:... Chandan Egbert

07:23 pm Issue #346: Undeclared svBitVecVal

Please see attached example. Use "sh doit.sh" to verilate and compile. Chandan Egbert

07:21 pm Issue #288: Verilator does not pass tests on sparc

Hello,
I was talking to a Debian Developer today, and he suggested using Qemu, it can emulate a MIPS machine on a x8... Ahmed El-Mahmoudy

07:20 pm Issue #346 (Closed): Undeclared svBitVecVal

Verilator version: Verilator 3.812 2011/04/06 rev verilator_3_811-18-ga20b4f2
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When a module with a DPI-C expor... Chandan Egbert

04:49 pm Issue #341: Verilator signal value evaluation problem?

Thank you so much for kindly looking at the problem. I'm already aware of the fact that using non-blocking assignment... Amin Firoozshahian

03:51 am Issue #288: Verilator does not pass tests on sparc

BTW a VNC session or equivelent would be fine too, I don't mind if you need to look over my shoulder for security rea... Wilson Snyder

03:50 am Issue #288: Verilator does not pass tests on sparc

I fixed the compile warnings. If you can figure out how to get me a shell on a system that shows this I'll debug it,... Wilson Snyder

03:44 am Issue #341 (Closed): Verilator signal value evaluation problem?

Sorry for the delay in resolving this,
test.v needs to use <= assignment when generating the signals rst, external... Wilson Snyder

02:26 am Issue #342 (WillNotFix): verilator does not allow floating point number in defparam

Unfortunately I don't think will be supported until floating point numbers are supported, which is tracked in bug233.... Wilson Snyder

04/27/2011

01:08 pm Issue #288: Verilator does not pass tests on sparc

Toolchain differences:... Ahmed El-Mahmoudy

12:40 pm Issue #288: Verilator does not pass tests on sparc

I suspect that the cause of the failure is probably the toolchain changes, rather than the changes introduced in 3.812 Ahmed El-Mahmoudy

12:36 pm Issue #288: Verilator does not pass tests on sparc

Now verilator 3.812 has the same failure on powerpc architecture, did you change anything from 3.811 to 3.812 that mi... Ahmed El-Mahmoudy

04/23/2011

02:17 am Issue #342 (Closed): verilator does not allow floating point number in defparam

Altera's DDR3 IP contains the following line:
defparam controller_phy_inst.ALTDQDQS_INPUT_FREQ = 533.0;
verilat... Alex Solomatnikov

04/22/2011

05:18 pm Issue #341 (Closed): Verilator signal value evaluation problem?

In the following code, depending on whether you enable/disable either the display statement or dummy assignment, outp... Amin Firoozshahian