Activity
From 09/05/2011 to 10/04/2011
10/04/2011
- 01:27 pm Issue #395 (Assigned): Tristate pins again
- Currently all bits of a tristate bus need to be handled together. We'll work at improving this.
If you want to lo... - 01:24 pm Patch #397 (Resolved): Output --help text to stdout instead of stderr
- I see your point, stdout does seem the standard for gnu stuff.
Fixed in git towards 3.822. Also, fixed in git for ... - 12:52 pm Issue #396 (Resolved): autoconf warnings; was: Compilation problems
- autoconf warnings fixed in git head towards 3.822, thanks.
- 12:43 pm Patch #397 (Closed): Output --help text to stdout instead of stderr
- Please see the attached patch.
- 12:18 pm Issue #396: autoconf warnings; was: Compilation problems
- Oh wait, I know what happened. Instead of "autoconf", I issued at the beginning an "autoreconf" command, and that ove...
- 11:41 am Issue #396 (Assigned): autoconf warnings; was: Compilation problems
- Thanks for the patch. There's something else going on though, as via the .h files there's an include of config_build...
- 07:59 am Issue #396 (Closed): autoconf warnings; was: Compilation problems
- I am having trivial problems compiling Verilator's git head under Ubuntu 10.04, maybe I've missed something when conf...
10/01/2011
- 02:16 am Issue #395 (Closed): Tristate pins again
- I have a module that looks like this:...
09/29/2011
- 01:36 am Issue #233: Support real numbers
- $ceil and friends are now in git. BTW if you don't mind please file new bugs, otherwise I'm likely to miss the issue...
09/28/2011
- 12:42 am Issue #233: Support real numbers
- verilator does not support $ceil() function which is part of SystemVerilog standard:...
09/21/2011
- 11:30 pm Issue #393: %Error: Internal Error: ...: ../V3AstNodes.h:453: Unexpected Call
- To clarify, the RTL bug is that the signal "foo" in module "top" in the test case should be arrayed but is not.
- 10:05 pm Issue #393: %Error: Internal Error: ...: ../V3AstNodes.h:453: Unexpected Call
- Yes, we used this workaround.
It turns out there was a bug in Verilog and that was the reason verilator was failin... - 01:08 pm Issue #394 (Resolved): Verilated code doesn't compile on Visual Studio 2010
- Thanks for the pointer; simple enough to work around.
Fixed in git towards 3.822.
- 12:41 pm Issue #394 (Closed): Verilated code doesn't compile on Visual Studio 2010
- The problem is that @verilated.h@ uses @trunc@ and @round@ functions which are not defined on cmath.
See http://ww... - 11:37 am Issue #393: %Error: Internal Error: ...: ../V3AstNodes.h:453: Unexpected Call
- BTW a work around would probably be to simply tie the pin to zero
.oct_rz... - 11:37 am Issue #393: %Error: Internal Error: ...: ../V3AstNodes.h:453: Unexpected Call
- This assignment
1:2:2:2:2: ASSIGNW 0x5b92ad0 <e540369> {231} w1
1:2:2:2:2:1: ARRAYSEL 0x6a910c0 <e493720>... - 01:31 am Issue #393: %Error: Internal Error: ...: ../V3AstNodes.h:453: Unexpected Call
- Attached gziped files.
- 01:08 am Issue #393: %Error: Internal Error: ...: ../V3AstNodes.h:453: Unexpected Call
- Please, let me know how to send you those .tree files.
- 12:57 am Issue #393: %Error: Internal Error: ...: ../V3AstNodes.h:453: Unexpected Call
- Yes, oct_rzqin is an array pin, that is unconnected few levels below in the hierarchy.
The design uses multiple Alte... - 12:39 am Issue #393 (Assigned): %Error: Internal Error: ...: ../V3AstNodes.h:453: Unexpected Call
- In propagating constants between gates, there's some array (oct_rzqin?) that is constant in some way it has never enc...
09/20/2011
09/19/2011
- 02:51 pm Issue #392: Can't unroll generate for with complicated incrementer/init/test
- BTW, using a temporary parameter may work (I'm not sure if a genvar temporary would or wouldn't.)
genvar y;
... - 02:49 pm Issue #392 (Assigned): Can't unroll generate for with complicated incrementer/init/test
- Yes, the unroller is currently pretty stupid. I'll get to this, but it is unlikely to be in the next month as it is ...
- 02:43 pm Issue #392 (Feature): Can't unroll generate for with complicated incrementer/init/test
- The following for loop:...
- 12:20 pm Issue #389: Building Verilator with MinGW
- It is either what VERILATOR_ROOT is set to when you compile verilator itself, or more likely given what it shows, som...
- 12:04 pm Issue #389: Building Verilator with MinGW
- ...
09/15/2011
- 01:35 am Issue #288 (Closed): Verilator does not pass tests on sparc
- In 3.821
- 01:35 am Issue #374 (Closed): Casting doesn't work anymore
- 01:34 am Verilator 3.821 Released
- Verilator 3.821 2011/09/14
**** Fix PowerPC runtime error, bug288. [Ahmed El-Mahmoudy]
**** Fix internal error ...
09/14/2011
- 03:53 pm Issue #388 (Closed): Verilator does not pass tests on macosx
- Great! I'm a little surprised as the fix there was for nothing parsing at all on HPUX, but I'll take it!
- 03:49 pm Issue #388: Verilator does not pass tests on macosx
- Verilator works fine on MacOsx Lion with newest git version!! It both passed the tests, and is also working on my own...
- 10:45 am Issue #389: Building Verilator with MinGW
- That rule is found by make using VPATH; that in turn comes from the VERILATOR_ROOT setting.
So check both VERILATOR_... - 07:21 am Issue #389: Building Verilator with MinGW
- Ok. I made some progress with the root paths.
Now I have the following problem:...
09/13/2011
- 07:22 pm Issue #388: Verilator does not pass tests on macosx
- "git" instructions are under the "download" tab above this bug.
grep MODULE test_c/obj_dir/*.tree
All files ... - 07:04 pm Issue #388: Verilator does not pass tests on macosx
- Lion seems to have a broken ssh. VNC will likely be hard - I'm in Abu Dhabi and they tend to block VNC connections....
- 06:41 pm Issue #388: Verilator does not pass tests on macosx
- Removed --debugi 9 as well as --no-dump-tree
It ran pretty fast.
listing of test_c/obj_dir area:
Michaels-Ma... - 04:43 pm Issue #389: Building Verilator with MinGW
- Sorry I don't use MingGW and so don't know how it ties into make and all of that stuff. If you figure it out I'll ta...
- 04:31 pm Issue #389: Building Verilator with MinGW
- Another thing I just realized...
It's not a matter of unix/windows path. ifstream accepts both - It's a matter of ... - 04:14 pm Issue #389: Building Verilator with MinGW
- I can 'cat' the file:...
- 03:15 pm Issue #388: Verilator does not pass tests on macosx
- Also there was a bug fix for PowerPC that might be related, you can try the git version as that's unreleased.
- 03:13 pm Issue #388: Verilator does not pass tests on macosx
- Try removing the --debugi and --no-dump-tree entirely. It looks like it is parsing something, so when it finishes, p...
- 03:07 pm Issue #388: Verilator does not pass tests on macosx
- Thanks for your help on this!
Doing the above causes it to go into a very long loop of spitting out commands. Aft... - 12:00 pm Issue #389 (AskedReporter): Building Verilator with MinGW
- Can you 'cat' the file? Maybe it's read only.
Otherwise, use "gdb /home/amirg/verilator-3.820/test_c/../verilator... - 11:36 am Issue #389 (Closed): Building Verilator with MinGW
- Verilator was built successfully (but with warnings) with MinGW20110802 on Win-XP machine.
However, "make test" fail... - 12:25 am Issue #388 (Assigned): Verilator does not pass tests on macosx
- It looks like argv isn't working??
We'll have to do some back and forth to debug, first try
cd test_c
...
09/12/2011
09/08/2011
- 05:53 am Issue #384: verilator does not produce waveform/vcd for an unpacked array with >32 elements
- Thanks - I missed --trace-max-width option.
The only thing to add here is that description is somewhat confusing: ...
09/06/2011
- 04:54 pm Issue #385: Dpi exported tasks with array inputs don't compile.
- I was using 3.812, updating to 3.820 fixes large vectors. So I have things working with packing / unpacking across t...
09/05/2011
- 04:44 pm Issue #385 (Assigned): Dpi exported tasks with array inputs don't compile.
- DPI exports of wide vectors should be supported, there's a test case in test_regress/t/t_dpi_export.v; if you could m...
- 10:03 am Issue #385: Dpi exported tasks with array inputs don't compile.
- I'm actually trying to pass a transaction of 10s of bytes from C to Verilog. I was hoping to assemble the bytes in a...
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