Activity

From 02/02/2012 to 03/02/2012

10:31 pm Issue #446: Support for reading/assigning to packed arrays: BTW this will take at least a month, as it's behind supporting structs, since structs are making changes in the same ... Wilson Snyder
10:17 pm Issue #446 (Assigned): Support for reading/assigning to packed arrays: 1. Assigning packed arrays isn't currently supported, so this is a good test for that. We'll say that's what this bu... Wilson Snyder
06:40 pm Issue #446 (Closed): Support for reading/assigning to packed arrays: Hi,
Attached is a test for packed arrays. The test is based on the verilator test environment (except for the chec... Iztok Jeras

01:35 pm Issue #443: verilator hangs up on circular macro definition: In Verilog-Perl 3.314.
Wilson Snyder

02:54 am Issue #443 (Resolved): verilator hangs up on circular macro definition: The verilog preprocessor must be one of the most complicated things I've worked on relative to how simple one would _... Wilson Snyder

11:05 pm Issue #443 (Closed): verilator hangs up on circular macro definition: Test case:... Alex Solomatnikov

03:11 am Issue #431 (Closed): typedef inside module causes internal error: Closing until can get test.
Alternatively if this is blocking you, I can step through how to debug it.
Wilson Snyder

07:36 am Issue #431: typedef inside module causes internal error: Unfortunately, it looks like this error happens only when I compile the whole design. Even when I tried to compile a ... Alex Solomatnikov

12:10 am Issue #304 (Closed): What can cause: Internal Error: Non-cutable edge forms a loop: This issue was resolved with a workaround. Wilson Snyder

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