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Activity
From 03/21/2012 to 04/19/2012
04/19/2012
- 09:46 pm Issue #485 (Assigned): verilator does not detect if block name is used twice
- It has this warning but due to a bug misses it when under a FOR loop.
- 06:25 pm Issue #485 (Feature): verilator does not detect if block name is used twice
- Code:...
- 05:11 pm Issue #413: generate-conditional with short-circuited local expression
- Some more changes, following email discussion. This is now strictly IEEE 1800-2009. Short-circuiting is used only for...
04/16/2012
- 11:29 am Issue #484: issues handling unsized literals with x/z extending
- The comparison inv !== 1'bx will always be true, because people do x comparisons to check for uninitialized state in ...
- 08:00 am Patch #482: Enable doxygen analysis of Verilator source
- Thanks for this.
The HAS_DOT time is strange. The whole thing goes through on my workstation in a few minutes (3 y... - 06:51 am Issue #484: issues handling unsized literals with x/z extending
- Hi Wilson,
My expectation was that all x/z bits from variables and literals would be converted to zeros. This woul... - 12:18 am Issue #484: issues handling unsized literals with x/z extending
- Verilator is correct. It correctly does not warn on 'x, which expands to an arbitrary width. It does warn on 'hx, '...
04/15/2012
- 10:25 pm Issue #484 (NoFixNeeded): issues handling unsized literals with x/z extending
- Hi,
One of the issues is Verilator handles 'x as a 32bit value, so WIDTH errors had to be silenced.
The other iss... - 08:40 pm Issue #454 (Closed): --gdb flag does not work
- In 3.833.
- 08:39 pm Issue #456 (Closed): unnecessary %Warning-UNSIGNED: Comparison is constant due to unsigned arithm...
- In 3.833.
- 08:39 pm Issue #461 (Closed): genvar declaration inside generate
- In 3.833.
- 08:39 pm Issue #463 (Closed): operator += is not supported
- In 3.833.
- 08:39 pm Issue #469 (Closed): Internal Error: ../V3Width.cpp:1201: Unlinked
- In 3.833.
- 08:39 pm Issue #470 (Closed): Support modules which are never used with their default parameter values
- In 3.833.
- 08:39 pm Issue #475 (Closed): %Error: Internal Error: ...: ../V3Number.cpp:518: Real conversion on non rea...
- In 3.833.
- 08:38 pm Issue #477 (Closed): incorrect %Error: Selection index out of range
- In 3.833.
- 08:38 pm Issue #479 (Closed): %Error: ...: Exceeded limit of 1024 bits for any display arguments
- In 3.833.
- 08:38 pm Verilator 3.833 Released
- Verilator 3.833 2012/04/15
*** Support += and -= in standard for loops, bug463. [Alex Solomatnikov]
*** Fix... - 08:28 pm Issue #364 (Assigned): blocking & non-blocking assigns -- verilator issues error when no logical ...
- The fixed note should have mentioned it fixes only arrays used in this context. I'll leave the bug open until the mo...
- 07:45 pm Patch #482 (Closed): Enable doxygen analysis of Verilator source
- Pushed to git. I disabled HAS_DOT, as after an hour it was only maybe 20% done.
- 07:14 pm Patch #483: Additions to the internals documentation
- P.S. made some minor updates, the only major item is that one generally should use the methods defined in each AstXXY...
- 07:10 pm Patch #483 (Closed): Additions to the internals documentation
- In git towards 3.833.
BTW you can just "git ci" each of your change sets, then use "git format-patch" to make the ... - 06:36 pm Patch #482: Enable doxygen analysis of Verilator source
- I've used doxygen, it's good. There's a small set of doxygen comments in some of the include files, from stuff inher...
- 06:20 pm Patch #483 (Closed): Additions to the internals documentation
- I've added some more detail to the internals document. This is based on my recent coding experiences with Verilator, ...
- 06:04 pm Patch #482 (Closed): Enable doxygen analysis of Verilator source
- The attached patch provides "make doxygen" to generate a doxygen analysis of the Verilator C++ source.
Doxygen is ... - 05:52 pm Issue #413: generate-conditional with short-circuited local expression
- Updated patch, which has a modified TREEOP to generate short-circuited visitors. Various improvements to the C++ code...
04/14/2012
- 11:53 am Issue #413: generate-conditional with short-circuited local expression
- I added to git a t_dpi_shortcircuit test. It's currently disabled.
I also added a patch to do the emacs indentati...
04/13/2012
- 12:33 am Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
- I should add that in previous example variables are defined as simple vectors:...
04/12/2012
- 10:22 pm Patch #473: Set of SystemVerilog tests
- I committed t_array_query, t_sv_conditional and t_enum_methods. (Note renamed some.)
The enum one had this:
... - 08:01 pm Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
- Apparently, I was wrong - it sill does not work in some cases, e.g.:...
- 10:56 am Issue #413: generate-conditional with short-circuited local expression
- Great, I'm still digesting! I need to think about how to get what you want with the astgen visitors without actually...
- 10:47 am Issue #364 (Resolved): blocking & non-blocking assigns -- verilator issues error when no logical ...
- Yes, fixed in git towards 3.833.
- 10:21 am Patch #473: Set of SystemVerilog tests
- I've fixed t_sv_array_query.v. It is now a proper test of array query functions.
t_sv_enum_type_methods.v should h... - 12:57 am Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
- Is this issue resolved as part of DETECTARRAY issue fix?
Seems to compile and run correctly now.
04/11/2012
- 04:58 pm Issue #413: generate-conditional with short-circuited local expression
- Here is a patch to deal with this. It only affects generated @if@, since the test in generated @for@ loops is restric...
04/08/2012
- 10:15 pm Issue #481 (Duplicate): Support for SystemVerilog "interface"
- Thanks for the test, merged it into git.
Closing as the feature is tracked in bug102.
- 10:08 pm Issue #480 (Closed): Support for SystemVerilog "parameter type"
- Great, merged this into git, though renamed t_param_type to match the other param types.
Closing, as test merged, ... - 10:02 pm Issue #376: Support "parameter type"
- Iztok Jeras contributed a test, see bug480.
- 09:56 pm Issue #481 (Duplicate): Support for SystemVerilog "interface"
- Hi,
The SystemVerilog feature "interface" is not yet supported, I created a test for it. The interface in the exam... - 09:48 pm Issue #480 (Closed): Support for SystemVerilog "parameter type"
- Hi,
The SystemVerilog feature "Parameter type" is not yet supported, I created a test for it. The provided test cr...
04/06/2012
- 01:50 am Issue #479 (Resolved): %Error: ...: Exceeded limit of 1024 bits for any display arguments
- Fixed in git by weedly increasing the limit. There's two defines that can be changed to increase it to whatever is n...
- 12:59 am Issue #479 (Closed): %Error: ...: Exceeded limit of 1024 bits for any display arguments
- Source code (in lib):...
04/05/2012
- 01:56 am Issue #477 (Resolved): incorrect %Error: Selection index out of range
- If you comment out the u1 instantiation you will see it fails for u2 only. This is because u1 does have an index [7] ...
- 01:21 am Issue #478: %Error: ...: Internal: Blocking <= assignment in non-clocked block, should have conve...
- My last message was wrong and should be disregarded: in fact Error-BLKANDNBLK is related to different module.
- 01:07 am Issue #478: %Error: ...: Internal: Blocking <= assignment in non-clocked block, should have conve...
- In the BLKANDNBLK case, even though these are errors you can turn them off like you would a warning; this is because ...
- 01:03 am Issue #478: %Error: ...: Internal: Blocking <= assignment in non-clocked block, should have conve...
- After I tried to convert non-blocking assignments <= to blocking =, I get:...
- 12:24 am Issue #478: %Error: ...: Internal: Blocking <= assignment in non-clocked block, should have conve...
- There is also an error message in the same initial block about non-blocking assignment to an array...
- 12:18 am Issue #478 (Closed): %Error: ...: Internal: Blocking <= assignment in non-clocked block, should h...
- Source code looks like:...
04/04/2012
- 03:30 am Issue #477: incorrect %Error: Selection index out of range
- Not sure why you mentioned if(i==0) condition. Verilator compiles without errors if there is only 1 instantiation, e....
- 02:35 am Issue #477: incorrect %Error: Selection index out of range
- Verilator doesn't realize that rst_reg[i-1] when the the loop has i=0 can not execute due to the if(i==0) condition b...
- 01:42 am Issue #477 (Closed): incorrect %Error: Selection index out of range
- Test case:...
04/03/2012
- 10:15 pm Issue #476 (Feature): Support && inside sensitivity list
- That's not synthesizable and it's also a very rare construct, so as you already noted it's low on the list.
- 10:09 pm Issue #476 (Feature): Support && inside sensitivity list
- Source code:...
- 02:01 am Issue #475 (Resolved): %Error: Internal Error: ...: ../V3Number.cpp:518: Real conversion on non r...
- Conversion of real functions to constants was buggy.
Fixed in git towards 3.833.
- 01:14 am Issue #474: Support inserting package symbols underneath module symbols
- It looks like there is a related problem: localparam defined inside package cannot be used in function defined inside...
- 12:42 am Issue #475: %Error: Internal Error: ...: ../V3Number.cpp:518: Real conversion on non real number
- Test case:...
- 12:17 am Issue #475: %Error: Internal Error: ...: ../V3Number.cpp:518: Real conversion on non real number
- Please try to make a standalone test case that fails; the critical code here is what's in the ...'s. Also, in the en...
- 12:01 am Issue #475 (Closed): %Error: Internal Error: ...: ../V3Number.cpp:518: Real conversion on non rea...
- Source code:...
04/02/2012
- 11:43 pm Issue #474 (Feature): Support inserting package symbols underneath module symbols
- It really should say "unsupported". Currently imports are handled by pulling the symbols into the local module, whic...
- 11:00 pm Issue #474 (Closed): Support inserting package symbols underneath module symbols
- Source code line:...
- 11:17 am Issue #469 (Resolved): Internal Error: ../V3Width.cpp:1201: Unlinked
- Great, we'll mark this fixed with bug470.
- 05:05 am Issue #469: Internal Error: ../V3Width.cpp:1201: Unlinked
- Yes, I got:...
04/01/2012
- 11:39 am Issue #469: Internal Error: ../V3Width.cpp:1201: Unlinked
- When you run with "--debugi-V3LinkDot 9" do you get a message:
Dead module for 0x1825f70 (e.g. the MODULE from ... - 03:09 am Issue #469: Internal Error: ../V3Width.cpp:1201: Unlinked
- I rolled back the fix for bug470 and re-produced this issue:...
03/31/2012
- 08:03 pm Patch #473 (Assigned): Set of SystemVerilog tests
- Great step, good to have progress towards these tests.
t_sv_array_query.v is not a valid program - looks unfinishe... - 03:43 pm Patch #473 (Closed): Set of SystemVerilog tests
- M W Lund of Atmel has contributed the attached set of tests which exercise the synthesizable subset of SytemVerilog I...
03/28/2012
- 12:08 am Patch #451 (Closed): Additional test of DPI used to implement generic accessor functions
- Great, in git towards 3.833, thanks.
03/27/2012
- 05:41 pm Patch #451: Additional test of DPI used to implement generic accessor functions
- Apologies - fell off the stack.
New version attached as diff against current git HEAD (commit 996f48fcf0d44d1c385e...
03/25/2012
- 12:31 am Issue #469: Internal Error: ../V3Width.cpp:1201: Unlinked
- Indeed, after fix for bug470 this issue disappeared.
I will try to generate nodes later. - 12:29 am Issue #470: Support modules which are never used with their default parameter values
- Thanks for the fix! This was the last issue in the IP block, although I still have to try to compile all the libraries.
03/24/2012
- 07:56 pm Issue #470 (Resolved): Support modules which are never used with their default parameter values
- It occurred to me that I could just not do parameter expansion on modules that aren't used and leave the eliminating ...
- 03:49 pm Issue #470: Support modules which are never used with their default parameter values
- Unfortunately, this is really common in the IP code I am trying to compile with verilator, so it is not easy to hack ...
- 02:31 pm Patch #451: Additional test of DPI used to implement generic accessor functions
- Would you like to make the updates mentioned in the last post (the read only and self testing) so I could add this to...
- 02:30 pm Issue #469 (AskedReporter): Internal Error: ../V3Width.cpp:1201: Unlinked
- The unlinked error means the earlier link stage messed up and missed processing this node (the function). It's likel...
- 02:19 pm Issue #470 (Assigned): Support modules which are never used with their default parameter values
- This is because there is a division by 0 in the module before parameter expansion. At present Verilator needs "all-de...
- 01:21 am Issue #470: Support modules which are never used with their default parameter values
- If I change code to:...
- 01:15 am Issue #470 (Closed): Support modules which are never used with their default parameter values
- Code:...
03/23/2012
- 11:43 pm Issue #469: Internal Error: ../V3Width.cpp:1201: Unlinked
- Last message was incorrect - there is no "Can't find definition" error.
I ran under gdb and got backtrace just befor... - 09:48 pm Issue #469: Internal Error: ../V3Width.cpp:1201: Unlinked
- There is a workaround - inlining the function.
- 09:42 pm Issue #469 (Closed): Internal Error: ../V3Width.cpp:1201: Unlinked
- Code snippet:...
- 12:51 pm Issue #466 (Feature): Support wires with array declarations
- 12:50 pm Issue #461 (Resolved): genvar declaration inside generate
- Verilator fixed in git towards 3.833.
- 12:49 pm Issue #461: genvar declaration inside generate
- Verilog-Perl: Fixed in git towards 3.315.
- 02:37 am Issue #462 (Feature): Support tri0/tri1
- Shouldn't be too hard to support, but other tristate bugs seem to break the simple solution to this. When those are ...
- 02:20 am Issue #468 (Feature): Support primitive instantiations
- Primitives are not synthesizable and are very slow compared to writing good behavioral code and so are unlikely to be...
- 02:14 am Issue #468 (Feature): Support primitive instantiations
- Primitive definition:...
- 01:32 am Issue #467: Support old format $display ($time, "...")
- Another example:...
- 01:29 am Issue #467 (Feature): Support old format $display ($time, "...")
- Obviously Verilator currently expects a format string.
- 01:26 am Issue #461 (Assigned): genvar declaration inside generate
- 01:26 am Issue #461: genvar declaration inside generate
- This is a bug in verilog-perl also, I will fix it there with high priority first as it is supposed to accept everythi...
- 01:19 am Issue #467 (Feature): Support old format $display ($time, "...")
- Code:...
- 01:05 am Issue #466: Support wires with array declarations
- Note it works fine if it is a non-wire type, e.g. logic.
- 01:02 am Issue #463 (Resolved): operator += is not supported
- Trivially fixed as was an oversight; += worked in generate for.
Fixed in git towards 3.833.
- 12:39 am Issue #465 (Closed): non-blocking assignment of '0 literal with delay causes syntax error
- This is a duplicate of bug406.
- 12:18 am Issue #466 (Feature): Support wires with array declarations
- Code:...
03/22/2012
- 11:52 pm Issue #465 (Closed): non-blocking assignment of '0 literal with delay causes syntax error
- Code:...
- 11:32 pm Issue #355: Support '{...}
- Another example:...
- 11:06 pm Issue #464 (NoFixNeeded): $fopen is not supported
- You need to use the more recent MCD replacement:
$fopen("aaa.tr","w"); - 11:03 pm Issue #464 (NoFixNeeded): $fopen is not supported
- In Altera's IP code:...
- 10:46 pm Issue #463: operator += is not supported
- Obviously, low priority - the code can be easily fixed.
- 10:45 pm Issue #461: genvar declaration inside generate
- Obviously, low priority - the code can be easily fixed.
- 10:44 pm Issue #463 (Closed): operator += is not supported
- In Altera's IP:...
- 10:26 pm Issue #462 (Closed): Support tri0/tri1
- tri0/tri1 - in Altera's IP.
Can they be supported given that verilator supports inouts?
- 10:13 pm Issue #461 (Closed): genvar declaration inside generate
- The following code in Altera's IP:...
03/21/2012
- 12:38 am Issue #460 (Feature): Support enumeration type methods
- Not too hard to support, but needs a run-time lookup table. Will do after structs, as need other changes in same are...
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