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Activity
From 03/26/2012 to 04/24/2012
04/24/2012
- 11:40 pm Issue #491: %Error: ...: Expected integral (non-real) input to ITORD
- The workaround that worked for this:...
- 10:36 pm Issue #491: %Error: ...: Expected integral (non-real) input to ITORD
- I should add that function definition is under package:...
- 10:24 pm Issue #491 (Closed): %Error: ...: Expected integral (non-real) input to ITORD
- Not a very descriptive error message, sounds like an internal error message about verilator limitation.
Source cod... - 10:10 pm Issue #490: %Error: Internal Error: ...: ../V3Link.cpp:113: Symbol table not found looking up symbol
- Yes, it's choking on the package import.
- 09:44 pm Issue #490 (Closed): %Error: Internal Error: ...: ../V3Link.cpp:113: Symbol table not found looki...
- Got internal error (without any regular errors):...
- 07:21 pm Issue #467: Support old format $display ($time, "...")
- More $display() cases that don't work with verilator:...
- 06:09 pm Issue #468: Support primitive instantiations
- BTW, the problem with the code above is that verilator can not parse anonymous primitive instantiation.
If instanc... - 01:46 pm Issue #487: Support short-circuiting of bitswise AND and OR
- Thanks for running the tests. I'll update my patch accordingly.
- 01:22 pm Issue #487: Support short-circuiting of bitswise AND and OR
- NC does print a warning, but then passes and VCS passes identically, so this test doesn't prove the difference you in...
- 01:13 pm Issue #487: Support short-circuiting of bitswise AND and OR
- Sorry - I should have added, that is Verilator with my patch to enable bitwise AND short-circuiting with Verilog. It ...
- 01:10 pm Issue #487: Support short-circuiting of bitswise AND and OR
- As noted, I don't have VCS to check this, but I have reduced the test to just using bitwise-AND. This passes in Icaru...
- 12:44 pm Issue #487: Support short-circuiting of bitswise AND and OR
- Can you post a test that shows what you just said; namely it passes in VCS and fails in NC? (Warnings not being cons...
- 12:25 pm Issue #487: Support short-circuiting of bitswise AND and OR
- Hmmm. Things get more and more messy.
VCS appears to do bitwise constant folding, but evidently gets the wrong ans... - 11:12 am Issue #489 (Closed): declaration of input as tri1 causes an error
- Fixed in git for release with tri0/tri1.
- 10:49 am Issue #487: Support short-circuiting of bitswise AND and OR
- VCS fails with $stop at line 88. NC complains about bit-select out of bounds on 67 as the AND isn't short circuited....
- 08:15 am Issue #487: Support short-circuiting of bitswise AND and OR
- I have to confess that I don't have a copy of the 2005 standard, but the 2001 standard definitely leaves it up to the...
- 01:24 am Issue #489 (Closed): declaration of input as tri1 causes an error
- Source code:...
- 12:15 am Issue #488: Support pmos, etc.
- P.S. nmos and pmos only for now as for what I can tell rnmos and rpmos are generally used where strengths are require...
- 12:14 am Issue #488 (Resolved): Support pmos, etc.
- You're right, for the limited stuff supported they might as well be aliases.
Fixed in git towards 3.840+.
04/23/2012
- 11:26 pm Issue #488 (Closed): Support pmos, etc.
- Given that verilator supports tri-states better now, would it be easy to support pmos and others?
Also, it seems t... - 11:16 pm Issue #487 (Assigned): Support short-circuiting of bitswise AND and OR
- Isn't short-circuiting optional in Verilog-2001? Either way I do not believe Verilator should do anything different ...
- 02:04 pm Issue #487 (Assigned): Support short-circuiting of bitswise AND and OR
- Verilog 2001 (and I believe 2005) allows considerable flexibility in short-circuiting. IEEE 1364-2001, section 4.1.4 ...
04/22/2012
- 02:45 am Issue #462 (Resolved): Support tri0/tri1
- Fixed in git towards 3.840+.
- 02:45 am Issue #395 (Closed): Tristate pins again
- Fixed in git towards 3.840+.
- 02:44 am Issue #56 (Closed): Inout signals within modules don't propogate correctly.
- Fixed in git towards 3.840+.
- 02:44 am Issue #54 (Resolved): Tristates break when a child modules does has no driver
- Fixed in git towards 3.840+.
- 02:43 am Issue #51 (Resolved): Mixing tristate and low-Z drivers. Error Msg unclear.
- Fixed in git towards 3.840+.
04/21/2012
- 05:00 pm Patch #486 (Closed): Update testing docs
- Committed. Bonus points for writing documentation!
I think I'd like to leave the main documentation to focus on w...
04/20/2012
- 05:23 pm Patch #486 (Closed): Update testing docs
- I've updated the BUGS section of the Verilator user guide based on my recent experiences, to help those writing tests...
- 02:55 am Issue #413 (Resolved): generate-conditional with short-circuited local expression
- I ran "make test" and it showed two failures t_lint_unused_bad and t_lint_syncasyncnet_bad, related to short circuiti...
04/19/2012
- 09:46 pm Issue #485 (Assigned): verilator does not detect if block name is used twice
- It has this warning but due to a bug misses it when under a FOR loop.
- 06:25 pm Issue #485 (Feature): verilator does not detect if block name is used twice
- Code:...
- 05:11 pm Issue #413: generate-conditional with short-circuited local expression
- Some more changes, following email discussion. This is now strictly IEEE 1800-2009. Short-circuiting is used only for...
04/16/2012
- 11:29 am Issue #484: issues handling unsized literals with x/z extending
- The comparison inv !== 1'bx will always be true, because people do x comparisons to check for uninitialized state in ...
- 08:00 am Patch #482: Enable doxygen analysis of Verilator source
- Thanks for this.
The HAS_DOT time is strange. The whole thing goes through on my workstation in a few minutes (3 y... - 06:51 am Issue #484: issues handling unsized literals with x/z extending
- Hi Wilson,
My expectation was that all x/z bits from variables and literals would be converted to zeros. This woul... - 12:18 am Issue #484: issues handling unsized literals with x/z extending
- Verilator is correct. It correctly does not warn on 'x, which expands to an arbitrary width. It does warn on 'hx, '...
04/15/2012
- 10:25 pm Issue #484 (NoFixNeeded): issues handling unsized literals with x/z extending
- Hi,
One of the issues is Verilator handles 'x as a 32bit value, so WIDTH errors had to be silenced.
The other iss... - 08:40 pm Issue #454 (Closed): --gdb flag does not work
- In 3.833.
- 08:39 pm Issue #456 (Closed): unnecessary %Warning-UNSIGNED: Comparison is constant due to unsigned arithm...
- In 3.833.
- 08:39 pm Issue #461 (Closed): genvar declaration inside generate
- In 3.833.
- 08:39 pm Issue #463 (Closed): operator += is not supported
- In 3.833.
- 08:39 pm Issue #469 (Closed): Internal Error: ../V3Width.cpp:1201: Unlinked
- In 3.833.
- 08:39 pm Issue #470 (Closed): Support modules which are never used with their default parameter values
- In 3.833.
- 08:39 pm Issue #475 (Closed): %Error: Internal Error: ...: ../V3Number.cpp:518: Real conversion on non rea...
- In 3.833.
- 08:38 pm Issue #477 (Closed): incorrect %Error: Selection index out of range
- In 3.833.
- 08:38 pm Issue #479 (Closed): %Error: ...: Exceeded limit of 1024 bits for any display arguments
- In 3.833.
- 08:38 pm Verilator 3.833 Released
- Verilator 3.833 2012/04/15
*** Support += and -= in standard for loops, bug463. [Alex Solomatnikov]
*** Fix... - 08:28 pm Issue #364 (Assigned): blocking & non-blocking assigns -- verilator issues error when no logical ...
- The fixed note should have mentioned it fixes only arrays used in this context. I'll leave the bug open until the mo...
- 07:45 pm Patch #482 (Closed): Enable doxygen analysis of Verilator source
- Pushed to git. I disabled HAS_DOT, as after an hour it was only maybe 20% done.
- 07:14 pm Patch #483: Additions to the internals documentation
- P.S. made some minor updates, the only major item is that one generally should use the methods defined in each AstXXY...
- 07:10 pm Patch #483 (Closed): Additions to the internals documentation
- In git towards 3.833.
BTW you can just "git ci" each of your change sets, then use "git format-patch" to make the ... - 06:36 pm Patch #482: Enable doxygen analysis of Verilator source
- I've used doxygen, it's good. There's a small set of doxygen comments in some of the include files, from stuff inher...
- 06:20 pm Patch #483 (Closed): Additions to the internals documentation
- I've added some more detail to the internals document. This is based on my recent coding experiences with Verilator, ...
- 06:04 pm Patch #482 (Closed): Enable doxygen analysis of Verilator source
- The attached patch provides "make doxygen" to generate a doxygen analysis of the Verilator C++ source.
Doxygen is ... - 05:52 pm Issue #413: generate-conditional with short-circuited local expression
- Updated patch, which has a modified TREEOP to generate short-circuited visitors. Various improvements to the C++ code...
04/14/2012
- 11:53 am Issue #413: generate-conditional with short-circuited local expression
- I added to git a t_dpi_shortcircuit test. It's currently disabled.
I also added a patch to do the emacs indentati...
04/13/2012
- 12:33 am Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
- I should add that in previous example variables are defined as simple vectors:...
04/12/2012
- 10:22 pm Patch #473: Set of SystemVerilog tests
- I committed t_array_query, t_sv_conditional and t_enum_methods. (Note renamed some.)
The enum one had this:
... - 08:01 pm Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
- Apparently, I was wrong - it sill does not work in some cases, e.g.:...
- 10:56 am Issue #413: generate-conditional with short-circuited local expression
- Great, I'm still digesting! I need to think about how to get what you want with the astgen visitors without actually...
- 10:47 am Issue #364 (Resolved): blocking & non-blocking assigns -- verilator issues error when no logical ...
- Yes, fixed in git towards 3.833.
- 10:21 am Patch #473: Set of SystemVerilog tests
- I've fixed t_sv_array_query.v. It is now a proper test of array query functions.
t_sv_enum_type_methods.v should h... - 12:57 am Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
- Is this issue resolved as part of DETECTARRAY issue fix?
Seems to compile and run correctly now.
04/11/2012
- 04:58 pm Issue #413: generate-conditional with short-circuited local expression
- Here is a patch to deal with this. It only affects generated @if@, since the test in generated @for@ loops is restric...
04/08/2012
- 10:15 pm Issue #481 (Duplicate): Support for SystemVerilog "interface"
- Thanks for the test, merged it into git.
Closing as the feature is tracked in bug102.
- 10:08 pm Issue #480 (Closed): Support for SystemVerilog "parameter type"
- Great, merged this into git, though renamed t_param_type to match the other param types.
Closing, as test merged, ... - 10:02 pm Issue #376: Support "parameter type"
- Iztok Jeras contributed a test, see bug480.
- 09:56 pm Issue #481 (Duplicate): Support for SystemVerilog "interface"
- Hi,
The SystemVerilog feature "interface" is not yet supported, I created a test for it. The interface in the exam... - 09:48 pm Issue #480 (Closed): Support for SystemVerilog "parameter type"
- Hi,
The SystemVerilog feature "Parameter type" is not yet supported, I created a test for it. The provided test cr...
04/06/2012
- 01:50 am Issue #479 (Resolved): %Error: ...: Exceeded limit of 1024 bits for any display arguments
- Fixed in git by weedly increasing the limit. There's two defines that can be changed to increase it to whatever is n...
- 12:59 am Issue #479 (Closed): %Error: ...: Exceeded limit of 1024 bits for any display arguments
- Source code (in lib):...
04/05/2012
- 01:56 am Issue #477 (Resolved): incorrect %Error: Selection index out of range
- If you comment out the u1 instantiation you will see it fails for u2 only. This is because u1 does have an index [7] ...
- 01:21 am Issue #478: %Error: ...: Internal: Blocking <= assignment in non-clocked block, should have conve...
- My last message was wrong and should be disregarded: in fact Error-BLKANDNBLK is related to different module.
- 01:07 am Issue #478: %Error: ...: Internal: Blocking <= assignment in non-clocked block, should have conve...
- In the BLKANDNBLK case, even though these are errors you can turn them off like you would a warning; this is because ...
- 01:03 am Issue #478: %Error: ...: Internal: Blocking <= assignment in non-clocked block, should have conve...
- After I tried to convert non-blocking assignments <= to blocking =, I get:...
- 12:24 am Issue #478: %Error: ...: Internal: Blocking <= assignment in non-clocked block, should have conve...
- There is also an error message in the same initial block about non-blocking assignment to an array...
- 12:18 am Issue #478 (Closed): %Error: ...: Internal: Blocking <= assignment in non-clocked block, should h...
- Source code looks like:...
04/04/2012
- 03:30 am Issue #477: incorrect %Error: Selection index out of range
- Not sure why you mentioned if(i==0) condition. Verilator compiles without errors if there is only 1 instantiation, e....
- 02:35 am Issue #477: incorrect %Error: Selection index out of range
- Verilator doesn't realize that rst_reg[i-1] when the the loop has i=0 can not execute due to the if(i==0) condition b...
- 01:42 am Issue #477 (Closed): incorrect %Error: Selection index out of range
- Test case:...
04/03/2012
- 10:15 pm Issue #476 (Feature): Support && inside sensitivity list
- That's not synthesizable and it's also a very rare construct, so as you already noted it's low on the list.
- 10:09 pm Issue #476 (Feature): Support && inside sensitivity list
- Source code:...
- 02:01 am Issue #475 (Resolved): %Error: Internal Error: ...: ../V3Number.cpp:518: Real conversion on non r...
- Conversion of real functions to constants was buggy.
Fixed in git towards 3.833.
- 01:14 am Issue #474: Support inserting package symbols underneath module symbols
- It looks like there is a related problem: localparam defined inside package cannot be used in function defined inside...
- 12:42 am Issue #475: %Error: Internal Error: ...: ../V3Number.cpp:518: Real conversion on non real number
- Test case:...
- 12:17 am Issue #475: %Error: Internal Error: ...: ../V3Number.cpp:518: Real conversion on non real number
- Please try to make a standalone test case that fails; the critical code here is what's in the ...'s. Also, in the en...
- 12:01 am Issue #475 (Closed): %Error: Internal Error: ...: ../V3Number.cpp:518: Real conversion on non rea...
- Source code:...
04/02/2012
- 11:43 pm Issue #474 (Feature): Support inserting package symbols underneath module symbols
- It really should say "unsupported". Currently imports are handled by pulling the symbols into the local module, whic...
- 11:00 pm Issue #474 (Closed): Support inserting package symbols underneath module symbols
- Source code line:...
- 11:17 am Issue #469 (Resolved): Internal Error: ../V3Width.cpp:1201: Unlinked
- Great, we'll mark this fixed with bug470.
- 05:05 am Issue #469: Internal Error: ../V3Width.cpp:1201: Unlinked
- Yes, I got:...
04/01/2012
- 11:39 am Issue #469: Internal Error: ../V3Width.cpp:1201: Unlinked
- When you run with "--debugi-V3LinkDot 9" do you get a message:
Dead module for 0x1825f70 (e.g. the MODULE from ... - 03:09 am Issue #469: Internal Error: ../V3Width.cpp:1201: Unlinked
- I rolled back the fix for bug470 and re-produced this issue:...
03/31/2012
- 08:03 pm Patch #473 (Assigned): Set of SystemVerilog tests
- Great step, good to have progress towards these tests.
t_sv_array_query.v is not a valid program - looks unfinishe... - 03:43 pm Patch #473 (Closed): Set of SystemVerilog tests
- M W Lund of Atmel has contributed the attached set of tests which exercise the synthesizable subset of SytemVerilog I...
03/28/2012
- 12:08 am Patch #451 (Closed): Additional test of DPI used to implement generic accessor functions
- Great, in git towards 3.833, thanks.
03/27/2012
- 05:41 pm Patch #451: Additional test of DPI used to implement generic accessor functions
- Apologies - fell off the stack.
New version attached as diff against current git HEAD (commit 996f48fcf0d44d1c385e...
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