Verilator

05/21/2012

10:45 pm Issue #517 (Feature): Constant expression in generated block index not recognized

Wilson Snyder

10:45 pm Issue #517: Constant expression in generated block index not recognized

Link at present is a textual match, and it can't resolve cross-module references statically unless they are a constan... Wilson Snyder

10:42 pm Patch #515 (Closed): Test for System Verilog enumeration methods

Great, committed.
Wilson Snyder

02:10 pm Issue #517: Constant expression in generated block index not recognized

Investigating further, the problem is that this is a very early pass. So in fact even a plain constant parameter will... Jeremy Bennett

12:50 pm Issue #517 (Feature): Constant expression in generated block index not recognized

The following code fails to recognize the constant expression used as index into an array of generated module instanc... Jeremy Bennett

12:23 pm Patch #515: Test for System Verilog enumeration methods

Please pull an updated version from https://github.com/jeremybennett/verilator/tree/sv-enum-test.
The intention wa... Jeremy Bennett

05/17/2012

05:49 pm Issue #516 (Closed): suppress multiple warnings for the same issue

In complex designs with multiple instances of the same module, verilator generates multiple warnings for the same iss... Alex Solomatnikov

02:19 am Issue #511 (Resolved): signed/unsigned mixed calculation with WIDTH warning off

Fixed in git towards 3.840++.
Wilson Snyder

05/16/2012

11:31 pm Issue #513 (Resolved): Loop causes internal error

Better error message, fixed in git towards 3.900+.
Wilson Snyder

10:39 pm Patch #473 (Closed): Set of SystemVerilog tests

Merged to git.
Minor changes: removed trailing whitespace, removed some empty comment sections, added unsupported(... Wilson Snyder

10:18 pm Patch #515 (AskedReporter): Test for System Verilog enumeration methods

Thanks for the test.
This test needs to pass on VCS, NC or another simulator first. All complain "localparam t_pi... Wilson Snyder

04:35 pm Patch #515 (Closed): Test for System Verilog enumeration methods

System Verilog provides a set of methods for operating on enumerations. This new test, @t_sv_enum_type_methods.pl@, e... Jeremy Bennett

11:08 am Patch #473: Set of SystemVerilog tests

I've done some more work on the enum, and will submit a separate issue with a new test to cover some of the enum oper... Jeremy Bennett

05/15/2012

11:26 pm Issue #514 (Closed): Tristate causes error (in graph, not converted)

Yup, missed case in recent tristate changes. Fixed in git.
Wilson Snyder

06:02 pm Issue #495 (Closed): %Error: ...: Unsupported LHS tristate construct: NOT

Bug reporting should have closed this when the duplicate bug494 closed.
Wilson Snyder

02:26 pm Issue #514 (Closed): Tristate causes error (in graph, not converted)

Probably a result of recent upgrades to tristate handling, this reportedly worked in the past.... Jeremy Bennett

05/11/2012

04:21 pm Issue #355: Support '{...}

Hi,
This feature is now called "Assignment patterns". In addition to arrays and structures it can be used on 1D ve... Iztok Jeras

12:41 am Issue #513: Loop causes internal error

These would have gotten a BLKSEQ warning, but BLKSEQ is a lint-style-only warning.
Looks like the loop detection l... Wilson Snyder

05/10/2012

10:33 pm Issue #513: Loop causes internal error

I'm not sure how to best report this error, as the code requires an event driven simulator. Perhaps as a multidriven... Wilson Snyder

03:03 pm Issue #513 (Closed): Loop causes internal error

The following code has a loop dependency between the first two always blocks. It should execute to completion on the ... Jeremy Bennett

07:14 am Issue #509: Better error when illegal bit select of array

Thanks for the clarification. I had misread section 7.4.3 of the IEEE 1800-2009. This sort of assignment is only perm... Jeremy Bennett

12:34 am Issue #512 (Closed): %Error: ...: Unsupported tristate construct: BEGIN 'genblk5'

Thanks for the case; fixed in git.
Wilson Snyder

05/09/2012

09:26 pm Issue #512: %Error: ...: Unsupported tristate construct: BEGIN 'genblk5'

Test case:... Alex Solomatnikov

11:00 am Issue #512: %Error: ...: Unsupported tristate construct: BEGIN 'genblk5'

Can you attach a complete testcase? There must be tristate generating or under that statement. Wilson Snyder

04:14 am Issue #512 (Closed): %Error: ...: Unsupported tristate construct: BEGIN 'genblk5'

Source code:... Alex Solomatnikov

02:48 am Issue #511: signed/unsigned mixed calculation with WIDTH warning off

You'll note Verilator gave a WIDTH warning about this; you must have turned that warning off. When it has to width e... Wilson Snyder

01:56 am Issue #499 (Resolved): %Error: Internal Error: ...: ../V3Slice.cpp:418: Couldn't find a VarRef on...

I think this is fixed, but it uncovered some complicated issues requiring a large fix that might have broken somethin... Wilson Snyder

01:54 am Issue #510 (Resolved): Error with unsized elements in tristate select

Fixed in git. This included a major tristate change, so it might have broken something else.
Wilson Snyder

01:43 am Issue #511 (Closed): signed/unsigned mixed calculation with WIDTH warning off

I think signed/unsigned mixed calculation is wrong.
Sample code is below.
module mod(A);
output [7:0] ... junji hashimoto

05/08/2012

09:45 pm Issue #509 (Assigned): Better error when illegal bit select of array

This code is illegal, you're using an array of wires to assign a constant. This code fails on other simulators too.
... Wilson Snyder

09:43 pm Issue #508 (NoFixNeeded): Bit select of constant fails

a is a scalar. IEEE says it's illegal to select a scalar, so verilator is correct.
I committed this as a negative... Wilson Snyder

11:20 am Issue #510 (Closed): Error with unsized elements in tristate select

The following code fails:... Jeremy Bennett

07:56 am Issue #508: Bit select of constant fails

I should have added that if I change the declaration of b to... Jeremy Bennett

07:52 am Issue #509 (Assigned): Better error when illegal bit select of array

The following code fails with an internal error:... Jeremy Bennett

07:33 am Issue #508 (NoFixNeeded): Bit select of constant fails

The following code fails:... Jeremy Bennett

05/05/2012

03:39 pm Issue #506: Support SystemVerilog string initializations

It seems verilator does not support strings in general - I commented out that string initialization and it still gene... Alex Solomatnikov

11:40 am Issue #506 (Feature): Support SystemVerilog string initializations

Verilator currently only supports 'string' as part of a DPI export/import. It should at least throw an error, if not... Wilson Snyder

04:45 am Issue #506 (Feature): Support SystemVerilog string initializations

I tried to compile Altera's DDR3 controller and testbench with Micron's DDR3 DRAM model (Altera's DRAM model does not... Alex Solomatnikov

05/04/2012

02:00 am Issue #505 (Resolved): %Error: ...: Expecting expression to be constant, but can't determine cons...

Localparams weren't allowed in constant functions.
Fixed in git towards 3.840+.
P.S. if you could please create... Wilson Snyder

01:04 am Issue #505 (Closed): %Error: ...: Expecting expression to be constant, but can't determine consta...

Source code:... Alex Solomatnikov

12:23 am Issue #474: Support inserting package symbols underneath module symbols

Another example:... Alex Solomatnikov

05/03/2012

01:09 am Issue #446 (Feature): Support for reading/assigning to packed arrays

Wilson Snyder

01:04 am Issue #500 (Closed): Confusing error message with $fscanf() vs $display()

Decided it will just print "$display-like function format" so it's a hint. If someone else wants to do the plumbing ... Wilson Snyder

12:54 am Issue #501 (Resolved): Real data type lost/Expected real input to RTOIS

"input x" then "real x" wasn't handled while "input real x" worked ok; thus it thought it was an integer and caused t... Wilson Snyder

05/02/2012

02:06 am Issue #499 (Assigned): %Error: Internal Error: ...: ../V3Slice.cpp:418: Couldn't find a VarRef on...

Haven't forgotten about this, while the assertion itself is simple it uncovered a complicated issue.
Wilson Snyder

04/28/2012

02:37 am Issue #500 (Assigned): Confusing error message with $fscanf() vs $display()

The message is just hardcoded and doesn't bother to indicate the right call.
Anyhow %z isn't supported as 4 state ... Wilson Snyder

02:04 am Issue #501 (Closed): Real data type lost/Expected real input to RTOIS

Source code:... Alex Solomatnikov

01:58 am Issue #500: Confusing error message with $fscanf() vs $display()

The same thing for $fwrite():... Alex Solomatnikov

01:55 am Issue #500 (Closed): Confusing error message with $fscanf() vs $display()

Source code:... Alex Solomatnikov

01:36 am Issue #499: %Error: Internal Error: ...: ../V3Slice.cpp:418: Couldn't find a VarRef on the LHSP o...

gdb backtrace:... Alex Solomatnikov

01:15 am Issue #499 (Closed): %Error: Internal Error: ...: ../V3Slice.cpp:418: Couldn't find a VarRef on t...

After bug498 fix, I am getting this internal error.
Source code:... Alex Solomatnikov

04/27/2012

11:41 pm Issue #498 (Closed): %Error: Internal Error: ...v:60: ../V3SymTable.h:60: Inserting two symbols w...

Fixed in git, related to recent changes.
Wilson Snyder

09:56 pm Issue #181: Support struct and union

Was planning on being done next month, but someone keeps finding tristate bugs ;)
Wilson Snyder

09:54 pm Issue #498: %Error: Internal Error: ...v:60: ../V3SymTable.h:60: Inserting two symbols with same ...

gdb backtrace:... Alex Solomatnikov

09:23 pm Issue #498 (Closed): %Error: Internal Error: ...v:60: ../V3SymTable.h:60: Inserting two symbols w...

The error is on the following line:... Alex Solomatnikov

08:48 pm Issue #181: Support struct and union

Any estimates for when the first step would be implemented? Alex Solomatnikov

07:02 am Issue #495: %Error: ...: Unsupported LHS tristate construct: NOT

Yes, I rebuilt it twice and this error still occurs.
In your test the wires connected to tri0/tri1 inputs are all ... Alex Solomatnikov

02:33 am Issue #58 (NotEnoughInfo): Use of // verilator public with inout causes error

We'll address this with dpi functions if it comes up again.
Wilson Snyder

02:32 am Issue #55 (Resolved): Tristate: Tracing an inout signal is broken

Fixed as part of tristate changes, towards 3.840+.
Wilson Snyder

02:31 am Issue #491 (Resolved): %Error: ...: Expected integral (non-real) input to ITORD

Easy enough thanks to your good test case.
Fixed in git towards 3.840.
Wilson Snyder

02:00 am Issue #495: %Error: ...: Unsupported LHS tristate construct: NOT

Sure you rebuilt? test_regress/t/t_tri_unconn.v has this case, which failed before the fix and not now. Otherwise p... Wilson Snyder

01:56 am Issue #495: %Error: ...: Unsupported LHS tristate construct: NOT

Still getting the same error on the same line after fix for bug494:... Alex Solomatnikov

01:42 am Issue #491: %Error: ...: Expected integral (non-real) input to ITORD

Test case:... Alex Solomatnikov

01:12 am Issue #494 (Closed): seg. fault and %Error: ...: Unsupported tristate port expression: CONST '1'h0'

Wilson Snyder

01:12 am Issue #494: seg. fault and %Error: ...: Unsupported tristate port expression: CONST '1'h0'

Fixed in git. Closing as related to recent tristate changes.
Wilson Snyder

12:40 am Issue #478 (Resolved): %Error: ...: Internal: Blocking <= assignment in non-clocked block, should...

Added a new INITIALDLY warning you can suppress if you wish.
Fixed in git towards 3.840++.
Wilson Snyder

12:36 am Issue #495 (Duplicate): %Error: ...: Unsupported LHS tristate construct: NOT

Wilson Snyder

04/26/2012

11:27 pm Issue #491: %Error: ...: Expected integral (non-real) input to ITORD

I think I'm going to need a small testcase to reproduce this, as I can't seem to recreate it. Your debug dump is ve... Wilson Snyder

11:15 pm Issue #484 (AskedReporter): issues handling unsized literals with x/z extending

If you want to update the test to match behavior as described above let me know.
Wilson Snyder

11:14 pm Issue #496 (Feature): Unsupported: tristate construct: ASSIGNDLY

Wilson Snyder

08:24 pm Issue #493: suppress useless width warning on string parameter comparisons

I think I've run into this before and I thought you only get width warnings when the parameter length is less than th... Joe Eiler

06:22 pm Issue #496: Unsupported: tristate construct: ASSIGNDLY

I think this is a behavioral model of some FPGA hard macro.
Is it possible to simply ignore delay and issue a warn... Alex Solomatnikov

11:17 am Issue #495 (Assigned): %Error: ...: Unsupported LHS tristate construct: NOT

Should be fixed when bug494 is.
Wilson Snyder

11:15 am Issue #496 (Assigned): Unsupported: tristate construct: ASSIGNDLY

I do not think it support delayed assignments without massive changes, but will think about it.
Obviously the manu... Wilson Snyder

11:11 am Patch #497: More updates to the internal documentation

_Now_ in git :)
Wilson Snyder

11:11 am Patch #497 (Closed): More updates to the internal documentation

Thanks, not in git.
Wilson Snyder

10:17 am Patch #497 (Closed): More updates to the internal documentation

I've fleshed out the section on .tree files to list all the flags that may appear in the common node dump fields, exp... Jeremy Bennett

05:39 am Issue #494: seg. fault and %Error: ...: Unsupported tristate port expression: CONST '1'h0'

It seems that in this case and in bug495, bug496 verilator considers tri0/tri1 inputs as outputs.
Alex Solomatnikov

05:35 am Issue #494: seg. fault and %Error: ...: Unsupported tristate port expression: CONST '1'h0'

After seg. fault fix I got:... Alex Solomatnikov

05:31 am Issue #496 (Feature): Unsupported: tristate construct: ASSIGNDLY

Source code:... Alex Solomatnikov

05:20 am Issue #495 (Closed): %Error: ...: Unsupported LHS tristate construct: NOT

Source code line:... Alex Solomatnikov

04:56 am Issue #493: suppress useless width warning on string parameter comparisons

I think in this case parameter is declared unsized and is used only for configuration, e.g.:... Alex Solomatnikov

04:30 am Issue #494: seg. fault and %Error: ...: Unsupported tristate port expression: CONST '1'h0'

I thought that tri1/tri0 work as pull-up/pull-down, i.e. if the net is not driven then it would have 1/0 value instea... Alex Solomatnikov

03:03 am Issue #493: suppress useless width warning on string parameter comparisons

I can see how this is annoying but am not sure how to make a good general rule without disabling dangerous usages.
... Wilson Snyder

02:54 am Issue #494 (Assigned): seg. fault and %Error: ...: Unsupported tristate port expression: CONST '1...

Coredump is fixed in git.
The error remains for the moment. While this specific case (0 at the top and zero below... Wilson Snyder

01:55 am Issue #494 (Closed): seg. fault and %Error: ...: Unsupported tristate port expression: CONST '1'h0'

backtrace:... Alex Solomatnikov

01:36 am Issue #493 (Feature): suppress useless width warning on string parameter comparisons

Some libraries have code like this:... Alex Solomatnikov

04/25/2012

10:17 pm Issue #492 (Closed): Generate IF conditional does not correctly handle constant selections

In git; closing as never in formal release. Wilson Snyder

06:36 pm Issue #491: %Error: ...: Expected integral (non-real) input to ITORD

Here is gdb backtrace after bug490 fix:... Alex Solomatnikov

01:10 pm Issue #492 (Closed): Generate IF conditional does not correctly handle constant selections

The patch in Issue 413 to allow short-circuiting of conditionals introduced a bug in evaluating generate IF condition... Jeremy Bennett

02:06 am Issue #491: %Error: ...: Expected integral (non-real) input to ITORD

After I re-produced exactly the same source code as when this bug was filed, I got exactly the same errors.
So, fi... Alex Solomatnikov

01:53 am Issue #491: %Error: ...: Expected integral (non-real) input to ITORD

I am not sure. After bug490 fix, I got another set of errors on the same source file, including internal error:
<p... Alex Solomatnikov

01:22 am Issue #491: %Error: ...: Expected integral (non-real) input to ITORD

I believe this is related to bug490. Please try the git version.
Wilson Snyder

01:21 am Issue #490 (Resolved): %Error: Internal Error: ...: ../V3Link.cpp:113: Symbol table not found loo...

Missed case where need to do package before import.
Fixed in git towards 3.840+.
Wilson Snyder

12:43 am Issue #468: Support primitive instantiations

Added disabled test t_udp_noname. Anonymous UDPs will be a pain to support as removing the name results in a parser ... Wilson Snyder

04/24/2012

11:40 pm Issue #491: %Error: ...: Expected integral (non-real) input to ITORD

The workaround that worked for this:... Alex Solomatnikov

10:36 pm Issue #491: %Error: ...: Expected integral (non-real) input to ITORD

I should add that function definition is under package:... Alex Solomatnikov

10:24 pm Issue #491 (Closed): %Error: ...: Expected integral (non-real) input to ITORD

Not a very descriptive error message, sounds like an internal error message about verilator limitation.
Source cod... Alex Solomatnikov

10:10 pm Issue #490: %Error: Internal Error: ...: ../V3Link.cpp:113: Symbol table not found looking up symbol

Yes, it's choking on the package import.
Wilson Snyder

09:44 pm Issue #490 (Closed): %Error: Internal Error: ...: ../V3Link.cpp:113: Symbol table not found looki...

Got internal error (without any regular errors):... Alex Solomatnikov

07:21 pm Issue #467: Support old format $display ($time, "...")

More $display() cases that don't work with verilator:... Alex Solomatnikov

06:09 pm Issue #468: Support primitive instantiations

BTW, the problem with the code above is that verilator can not parse anonymous primitive instantiation.
If instanc... Alex Solomatnikov

01:46 pm Issue #487: Support short-circuiting of bitswise AND and OR

Thanks for running the tests. I'll update my patch accordingly. Jeremy Bennett

01:22 pm Issue #487: Support short-circuiting of bitswise AND and OR

NC does print a warning, but then passes and VCS passes identically, so this test doesn't prove the difference you in... Wilson Snyder

01:13 pm Issue #487: Support short-circuiting of bitswise AND and OR

Sorry - I should have added, that is Verilator with my patch to enable bitwise AND short-circuiting with Verilog. It ... Jeremy Bennett

01:10 pm Issue #487: Support short-circuiting of bitswise AND and OR

As noted, I don't have VCS to check this, but I have reduced the test to just using bitwise-AND. This passes in Icaru... Jeremy Bennett

12:44 pm Issue #487: Support short-circuiting of bitswise AND and OR

Can you post a test that shows what you just said; namely it passes in VCS and fails in NC? (Warnings not being cons... Wilson Snyder

12:25 pm Issue #487: Support short-circuiting of bitswise AND and OR

Hmmm. Things get more and more messy.
VCS appears to do bitwise constant folding, but evidently gets the wrong ans... Jeremy Bennett

11:12 am Issue #489 (Closed): declaration of input as tri1 causes an error

Fixed in git for release with tri0/tri1.
Wilson Snyder

10:49 am Issue #487: Support short-circuiting of bitswise AND and OR

VCS fails with $stop at line 88. NC complains about bit-select out of bounds on 67 as the AND isn't short circuited.... Wilson Snyder

08:15 am Issue #487: Support short-circuiting of bitswise AND and OR

I have to confess that I don't have a copy of the 2005 standard, but the 2001 standard definitely leaves it up to the... Jeremy Bennett

01:24 am Issue #489 (Closed): declaration of input as tri1 causes an error

Source code:... Alex Solomatnikov

12:15 am Issue #488: Support pmos, etc.

P.S. nmos and pmos only for now as for what I can tell rnmos and rpmos are generally used where strengths are require... Wilson Snyder

12:14 am Issue #488 (Resolved): Support pmos, etc.

You're right, for the limited stuff supported they might as well be aliases.
Fixed in git towards 3.840+.
Wilson Snyder

04/23/2012

11:26 pm Issue #488 (Closed): Support pmos, etc.

Given that verilator supports tri-states better now, would it be easy to support pmos and others?
Also, it seems t... Alex Solomatnikov

11:16 pm Issue #487 (Assigned): Support short-circuiting of bitswise AND and OR

Isn't short-circuiting optional in Verilog-2001? Either way I do not believe Verilator should do anything different ... Wilson Snyder

02:04 pm Issue #487 (Assigned): Support short-circuiting of bitswise AND and OR

Verilog 2001 (and I believe 2005) allows considerable flexibility in short-circuiting. IEEE 1364-2001, section 4.1.4 ... Jeremy Bennett

04/22/2012

02:45 am Issue #462 (Resolved): Support tri0/tri1

Fixed in git towards 3.840+.
Wilson Snyder

02:45 am Issue #395 (Closed): Tristate pins again

Fixed in git towards 3.840+.
Wilson Snyder

02:44 am Issue #56 (Closed): Inout signals within modules don't propogate correctly.

Fixed in git towards 3.840+.
Wilson Snyder

02:44 am Issue #54 (Resolved): Tristates break when a child modules does has no driver

Fixed in git towards 3.840+.
Wilson Snyder

02:43 am Issue #51 (Resolved): Mixing tristate and low-Z drivers. Error Msg unclear.

Fixed in git towards 3.840+.
Wilson Snyder