From 05/15/2012 to 06/13/2012
- 11:58 pm Issue #523 (WillNotFix): search for package on import
- When an import statement is encountered should verilator search for the package if it hasn't already seen it? Questa ...
- 03:19 am Issue #521 (Closed): Problem with -DVL_LEAK_CHECKS
- Fixed most leaks (rest should go away when other features go in).
When compiled with VL_LEAK_CHECKS, --debug-check...
- 02:59 am Issue #521: Problem with -DVL_LEAK_CHECKS
- This is fixed in git, the core dump was due to recent changes for structs.
The check does report many leaks though...
- 02:31 pm Issue #521 (Closed): Problem with -DVL_LEAK_CHECKS
- I enabled -DVL_LEAK_CHECKS (by uncommenting the line in src/Makefile_obj.in). Building Verilator failed with:
- 01:32 am Issue #516 (Resolved): suppress multiple warnings for the same issue
- 01:32 am Issue #516 (Assigned): suppress multiple warnings for the same issue
- Thought I'd knock this off in a few minutes, but forgot about multi line messages.
Anyhow fixed in git towards 3.9...
- 10:45 pm Issue #517 (Feature): Constant expression in generated block index not recognized
- 10:45 pm Issue #517: Constant expression in generated block index not recognized
- Link at present is a textual match, and it can't resolve cross-module references statically unless they are a constan...
- 10:42 pm Patch #515 (Closed): Test for System Verilog enumeration methods
- Great, committed.
- 02:10 pm Issue #517: Constant expression in generated block index not recognized
- Investigating further, the problem is that this is a very early pass. So in fact even a plain constant parameter will...
- 12:50 pm Issue #517 (Feature): Constant expression in generated block index not recognized
- The following code fails to recognize the constant expression used as index into an array of generated module instanc...
- 12:23 pm Patch #515: Test for System Verilog enumeration methods
- Please pull an updated version from https://github.com/jeremybennett/verilator/tree/sv-enum-test.
The intention wa...
- 05:49 pm Issue #516 (Closed): suppress multiple warnings for the same issue
- In complex designs with multiple instances of the same module, verilator generates multiple warnings for the same iss...
- 02:19 am Issue #511 (Resolved): signed/unsigned mixed calculation with WIDTH warning off
- Fixed in git towards 3.840++.
- 11:31 pm Issue #513 (Resolved): Loop causes internal error
- Better error message, fixed in git towards 3.900+.
- 10:39 pm Patch #473 (Closed): Set of SystemVerilog tests
- Merged to git.
Minor changes: removed trailing whitespace, removed some empty comment sections, added unsupported(...
- 10:18 pm Patch #515 (AskedReporter): Test for System Verilog enumeration methods
- Thanks for the test.
This test needs to pass on VCS, NC or another simulator first. All complain "localparam t_pi...
- 04:35 pm Patch #515 (Closed): Test for System Verilog enumeration methods
- System Verilog provides a set of methods for operating on enumerations. This new test, @t_sv_enum_type_methods.pl@, e...
- 11:08 am Patch #473: Set of SystemVerilog tests
- I've done some more work on the enum, and will submit a separate issue with a new test to cover some of the enum oper...
- 11:26 pm Issue #514 (Closed): Tristate causes error (in graph, not converted)
- Yup, missed case in recent tristate changes. Fixed in git.
- 06:02 pm Issue #495 (Closed): %Error: ...: Unsupported LHS tristate construct: NOT
- Bug reporting should have closed this when the duplicate bug494 closed.
- 02:26 pm Issue #514 (Closed): Tristate causes error (in graph, not converted)
- Probably a result of recent upgrades to tristate handling, this reportedly worked in the past....
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