Verilator - Usage

_FILE_OFFSET_BITS=64? fwrite stops at 2gb

Brad Parker

07/21/2010 11:45 am

1

Added by Wilson Snyder about 1 month ago
RE: _FILE_OFFSET_BITS=64? fwrite stops at 2gb

Issues with dual clock domains?

Nick Bowler

07/12/2010 02:27 pm

2

Added by Wilson Snyder about 1 month ago
RE: Issues with dual clock domains?

Running Program on Processor

Dan Snyder

06/18/2010 01:10 am

2

Added by Dan Snyder 3 months ago
RE: Running Program on Processor

Access Register Without Defining as Input or Output

Dan Snyder

06/07/2010 05:28 pm

7

Added by Dan Snyder 3 months ago
RE: Access Register Without Defining as Input or Output

Load Array With Binary Contents

Dan Snyder

06/03/2010 02:11 pm

6

Added by Wilson Snyder 3 months ago
RE: Load Array With Binary Contents

Efficient Usage of Verilog-Parameters

Stefan Wallentowitz

04/14/2010 06:15 pm

1

Added by Wilson Snyder 5 months ago
RE: Efficient Usage of Verilog-Parameters

Bitwise check

Nadav Banet

03/24/2010 07:15 pm

1

Added by Wilson Snyder 6 months ago
RE: Bitwise check

`default_nettype none gives error

Dominic Plunkett

02/23/2010 12:52 pm

3

Added by Wilson Snyder 7 months ago
RE: `default_nettype none gives error

Running verilator continuosly

Jakob Eriksson

01/07/2010 10:44 am

1

Added by Wilson Snyder 8 months ago
RE: Running verilator continuosly

Converting VCD file to LXT file during simulation

Rodney Sinclair

07/16/2009 04:26 pm

2

Added by Rodney Sinclair 8 months ago
RE: Converting VCD file to LXT file during simulation

Memory usage for gate sim

Guy Hutchison

12/19/2009 02:15 am

7

Added by Wilson Snyder 9 months ago
RE: Memory usage for gate sim

Using a verilated module multiple times

Christian Leber

12/20/2009 12:14 am

2

Added by Wilson Snyder 9 months ago
RE: Using a verilated module multiple times

glbl.GTS

Adolfo Sanchez

11/14/2009 05:22 am

1

Added by Wilson Snyder 10 months ago
RE: glbl.GTS

Verilator no make rule to make the Vfull_adder_ALL.a

Adolfo Sanchez

10/07/2009 04:53 am

1

Added by Wilson Snyder 11 months ago
RE: Verilator no make rule to make the Vfull_adder_ALL.a

Generated Clocks

Andreas Olofsson

08/26/2009 11:40 pm

1

Added by Wilson Snyder about 1 year ago
RE: Generated Clocks

forcing sc_in<sc_bin>

Theocharis Tsenis

07/29/2009 08:36 pm

1

Added by Wilson Snyder about 1 year ago
RE: forcing sc_in<sc_bit>

VCD dumping

Yariv Saliternik

05/27/2009 10:15 am

2

Added by Yariv Saliternik over 1 year ago
RE: VCD dumping

Specifying verilator options externally

Lane Brooks

05/08/2009 05:44 pm

1

Added by Wilson Snyder over 1 year ago
RE: Specifying verilator options externally

How to make /* Verilator lint_off WIDTH */ global?

Eric Wen

04/29/2009 05:20 pm

2

Added by Eric Wen over 1 year ago
RE: How to make /* Verilator lint_off WIDTH */ global?

Best way to debug a segmentation fault in Verilator?

Dimitris Nalbantis

04/22/2009 04:27 pm

1

Added by Wilson Snyder over 1 year ago
RE: Best way to debug a segmentation fault in Verilator?

Packaging and distributing Verilator generated source files for compile and reuse in a third party C++ simulation environment

Dimitris Nalbantis

04/16/2009 10:50 am

4

Added by Dimitris Nalbantis over 1 year ago
RE: Packaging and distributing Verilator generated source...

verilator task call problem

Andrea Foletto

04/07/2009 02:31 pm

1

Added by Wilson Snyder over 1 year ago
RE: verilator task call problem

Verilator best practice flow - Large designs bottom-up?

Yariv Saliternik

03/17/2009 10:28 am

5

Added by Wilson Snyder over 1 year ago
RE: Verilator best practice flow - Large designs bottom-up?

The need for speed

Yariv Saliternik

03/08/2009 06:34 pm

5

Added by Yariv Saliternik over 1 year ago
RE: The need for speed

Asynchronous Reset

Aki Niimura

02/25/2009 05:07 pm

2

Added by Aki Niimura over 1 year ago
RE: Asynchronous Reset