Usage - Verilator

Verilator Parser (bison) as standalone parser for SystemVerilog files?

Jan Seyler

01/13/2012 12:02 pm

5

Include file

Yehuda Singer

01/23/2012 10:04 am

3

Added by Wilson Snyder 13 days ago
RE: Include file

How to prevent the "Blocking assignments (=) in sequential (flop or latch) block" warning for temporary variables

R. Diez

01/19/2012 03:41 pm

2

Added by Wilson Snyder 16 days ago
RE: How to prevent the "Blocking assignments (=) in seque...

Passing an sformat-formatted string to a DPI function

R. Diez

11/14/2011 09:57 am

6

Added by vsevolod predtechensky about 1 month ago
RE: Passing an sformat-formatted string to a DPI function

Does Verilator do short-circuit expression evaluation?

R. Diez

12/15/2011 09:56 am

1

Added by Wilson Snyder about 1 month ago
RE: Does Verilator do short-circuit expression evaluation?

"suggest delayed assignments" warning for array assignments inside 'for' loops

R. Diez

12/14/2011 09:33 am

0

Calling $finish in an 'initial' section does not stop right away

R. Diez

12/07/2011 09:34 am

1

Added by Wilson Snyder about 1 month ago
RE: Calling $finish in an 'initial' section does not stop...

Verilator's error message format does not easily allow for standard tools to jump to the related source code file and line

R. Diez

10/27/2011 03:24 pm

4

Added by Wilson Snyder 3 months ago
RE: Verilator's error message format does not easily allo...

False BLKSEQ warning in case of a task call that occurs under the control of a clock edge

Hui Chen

10/21/2011 04:49 am

3

Added by Wilson Snyder 3 months ago
RE: False BLKSEQ warning in case of a task call that occu...

Tracing back a Segmentation Fault

Mike Denio

10/07/2011 02:07 pm

2

Added by Mike Denio 4 months ago
RE: Tracing back a Segmentation Fault

Bidirectional port slice problem

Chandan Egbert

09/20/2011 10:09 pm

0

Compiling verilog testbench

Hui Chen

09/07/2011 08:05 am

3

Added by Wilson Snyder 5 months ago
RE: Compiling verilog testbench

Debug zero-time loop

Guy Hutchison

08/30/2011 07:43 pm

4

Added by Wilson Snyder 5 months ago
RE: Debug zero-time loop

Getting started writing Verilator testbenches

Jim McPhillips

08/12/2011 09:59 pm

1

Added by Wilson Snyder 6 months ago
RE: Getting started writing Verilator testbenches

Code coverage in --cc mode

John Li

07/28/2011 07:58 am

4

Added by John Li 6 months ago
RE: Code coverage in --cc mode

Problem while compiling my VERILOG-A code

Robert Szwarc

07/05/2011 06:40 pm

7

Added by Wilson Snyder 7 months ago
RE: Problem while compiling my VERILOG-A code

Race between Verilator and SystemC?

Chandan Egbert

07/07/2011 12:22 am

1

Added by Wilson Snyder 7 months ago
RE: Race between Verilator and SystemC?

Tracing SystemC and verilated Verilog together

Chandan Egbert

05/13/2011 01:23 am

2

Added by Chandan Egbert 8 months ago
RE: Tracing SystemC and verilated Verilog together

Performance Issue with Fdisplay

Andy Wagner

03/26/2011 02:12 am

3

Added by Andy Wagner 11 months ago
RE: Performance Issue with Fdisplay

Is it possible to use type as a parameter?

Alex Solomatnikov

03/16/2011 07:39 pm

3

Added by Alex Solomatnikov 11 months ago
RE: Is it possible to use type as a parameter?

Error running Example C++ Execution from manual

Muhammad Ali

03/07/2011 08:44 pm

2

Added by Muhammad Ali 11 months ago
RE: Error running Example C++ Execution from manual

verilating/compiling modules into separate object files

Alex Solomatnikov

12/15/2010 01:39 am

6

Added by Wilson Snyder 11 months ago
RE: verilating/compiling modules into separate object files

UNOPTFLAT Error

Terry Chen

10/25/2010 04:32 pm

6

Added by Wilson Snyder 12 months ago
RE: UNOPTFLAT Error

testbench wrapper

Jiang Long

01/22/2011 12:29 am

6

Added by Jiang Long about 1 year ago
RE: testbench wrapper

Fault sims?

Donald 'Paddy' McCarthy

01/11/2011 05:30 pm

3

Added by Wilson Snyder about 1 year ago
RE: Fault sims?