[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  Schedule::Load
  SVN::S4
  Synopsys-modes
  SystemPerl
  Verilog-Pli
  Voneline
  Vregs
General Info
  Papers

Issues

If you wish to add a new issue, you must log in and create an account; "New Issue" will then appear in the menu bar. Sorry, but this was necessary to prevent form-filling spam.
Filters

Apply Clear

Toggle_check # Tracker Status Priority Subject Assignee Updated
432 IssueResolvedNormalInternal Error with large amount of UNOPTFLAT WarningsWilson Snyder01/27/2012 01:20 am
431 IssueAskedReporterNormaltypedef inside module causes internal errorWilson Snyder01/12/2012 12:51 am
424 IssueFeatureNormalMultiple problems encountered with parameter arrays12/15/2011 12:16 pm
421 IssueFeatureNormalAdd an option for a custom header commentJeremy Bennett11/17/2011 09:02 am
413 IssueFeatureNormalgenerate-conditional with short-circuited local expression11/15/2011 11:14 am
408 IssueAssignedNormalverilator generates incorrect C++ code when genvar is used incorrectly11/12/2011 01:11 pm
406 IssueFeatureNormaldelayed assignment of unsized constant failsJeremy Bennett11/29/2011 02:18 am
395 IssueAssignedNormalTristate pins againLane Brooks10/04/2011 01:27 pm
393 IssueAssignedNormal%Error: Internal Error: ...: ../V3AstNodes.h:453: Unexpected CallWilson Snyder09/21/2011 11:30 pm
392 IssueAssignedNormalCan't unroll generate for with complicated incrementerWilson Snyder09/19/2011 02:51 pm
385 IssueFeatureLowDpi exported tasks with array inputs don't compile.Wilson Snyder11/29/2011 03:13 am
380 IssueAssignedNormalSupport of VHDL93Sebastien Van Cauwenberghe08/10/2011 06:49 am
379 IssueFeatureNormalSupport dynamic memory new and delete08/10/2011 12:08 am
378 IssueFeatureNormalSupport properties and assertions08/10/2011 12:07 am
377 IssueFeatureNormalSupport classes and methods08/10/2011 12:06 am
376 IssueFeatureNormalSupport "parameter type"08/10/2011 12:03 am
366 IssueAssignedNormalUnsupported sensitivity of arrayed variables07/21/2011 11:31 am
365 IssueAssignedNormalbidrectional arrays not supported as module ports07/21/2011 11:33 am
364 IssueFeatureLowblocking & non-blocking assigns -- verilator issues error when no logical conflict exists07/07/2011 08:58 pm
355 IssueFeatureNormalverilator does not support '{...}12/14/2011 03:35 am
349 IssueAssignedLowlogical shift of signed valuesWilson Snyder05/15/2011 07:06 pm
337 IssueAssignedNormalCompile Issue with Large Design with Large I/O BuswidthWilson Snyder03/30/2011 11:22 am
285 IssueFeatureLowVerilator lint misses bogusly-typed assignment and generates invalid C++Wilson Snyder09/26/2010 11:15 am
236 IssueFeatureNormalSupport real event loop04/07/2010 01:26 pm
235 IssueFeatureNormalSupport fork-joins and time delays04/07/2010 01:27 pm

1 2 Next ยป (1-25/38) | Per page: 25, 100, 250

Also available in: Atom CSV