[logo] 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Gspice
  IPC::Locker
  Schedule::Load
  SVN::S4
  Synopsys-modes
  SystemPerl
  Verilog-Pli
  Voneline
  Vregs
General Info
  Book Tips
  Papers

Issues

If you wish to add a new issue, you must log in and create an account; "New Issue" will then appear in the menu bar. Sorry, but this was necessary to prevent form-filling spam.
Filters
Add filter:

Apply Clear

Toggle_check # Tracker Status Priority Subject Assigned to Updated
220 IssueAssignedNormalLatch issue with clock gating signalWilson Snyder03/10/2010 05:04 pm
217 IssueResolvedNormalMac OS X build issues with 3.800Wilson Snyder02/27/2010 01:06 am
216 IssueResolvedLow"make uninstall" not working properlyWilson Snyder02/08/2010 02:29 pm
207 IssueFeatureNormalSupport assignment between packed arrays with different dimensionsByron Bradley01/19/2010 08:43 pm
181 IssueFeatureNormalSupport struct and unionWilson Snyder11/10/2009 09:42 pm
102 IssueFeatureNormalSupport "interface" and "endinterface" keywordsByron Bradley02/04/2010 11:16 am
63 IssueNewNormalFalse Signal unoptimizable: circular logic warning01/30/2009 05:33 pm
58 IssueAssignedNormalUse of // verilator public with inout causes errorLane Brooks01/26/2009 06:22 pm
56 IssueAssignedNormalInout signals within modules don't propogate correctly.Lane Brooks01/23/2009 09:05 pm
55 IssueAssignedNormalTristate: Tracing an inout signal is brokenLane Brooks01/22/2009 08:39 pm
54 IssueAssignedLowTristates break when a child modules does has no driverLane Brooks10/28/2009 01:52 pm
51 IssueAssignedNormalMixing tristate and low-Z drivers. Error Msg unclear.Lane Brooks10/28/2009 01:52 pm
50 IssueFeatureNormalClock gating support?10/28/2009 01:51 pm

(1-13/13) | Per page: 25, 100, 250

Also available in: Atom CSV PDF