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Issues

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	#	Tracker	Status	Priority	Subject	Assignee	Updated
	651	Issue	Resolved	Normal	Different versions of GCC cause Verilator generated models to succeed or fail	Jeremy Bennett	05/24/2013 12:21 am
	650	Issue	Closed	Normal	"make test" runs out of processes	Wilson Snyder	05/24/2013 12:09 am
	639	Patch	Closed	Normal	Small improvements to internals documentation	Jeremy Bennett	04/28/2013 01:04 pm
	615	Issue	Closed	Normal	Regression test t_vpi_var fails		03/09/2013 09:51 pm
	611	Patch	Closed	Normal	Improvements to UNOPTFLAT reporting	Jeremy Bennett	03/09/2013 09:51 pm
	610	Issue	Closed	Normal	DETECTARRAY error on packed structures	Jeremy Bennett	03/09/2013 09:51 pm
	606	Issue	Closed	Normal	Mis-evaluation of typed parameter	Wilson Snyder	02/05/2013 03:22 am
	605	Issue	Closed	Normal	bit-select with :+ and :- fails with packed structures	Jeremy Bennett	01/18/2013 02:49 am
	603	Issue	Closed	Normal	Bit select from 1-bit parameter causes error	Wilson Snyder	02/05/2013 03:22 am
	600	Issue	Closed	Normal	Bit selection from struct causes internal error	Wilson Snyder	02/05/2013 03:21 am
	599	Issue	Closed	Normal	Local declarations should override package declarations from wildcard import	Wilson Snyder	01/10/2013 03:26 am
	592	Issue	Closed	Low	Support for export in package declarations		01/01/2013 02:19 pm
	591	Issue	Closed	Normal	Problem with nested package imports	Wilson Snyder	01/10/2013 03:26 am
	586	Issue	Closed	Normal	Use of package qualified parameters	Wilson Snyder	01/10/2013 03:26 am
	583	Issue	Closed	Normal	Bad dead-code elimination with parameterized module	Wilson Snyder	12/01/2012 09:41 pm
	580	Issue	Closed	Normal	--debug overrides preceding --dump-treei value	Jeremy Bennett	12/01/2012 09:42 pm
	578	Patch	NoFixNeeded	Normal	Short-circuit bitwise-AND and bitwise-OR (Verilog only)	Jeremy Bennett	11/14/2012 02:30 am
	576	Issue	Feature	Normal	generate/endgenerate should not be optional in Verilog 2001		11/14/2012 01:38 am
	570	Patch	Closed	Normal	Triggering initial edge from X	Jeremy Bennett	11/04/2012 12:25 am
	555	Patch	Closed	Normal	Tidy up DOT file output	Jeremy Bennett	08/27/2012 11:03 pm
	554	Patch	Closed	Normal	Updates to the internal documentation	Jeremy Bennett	08/27/2012 04:04 pm
	553	Patch	Closed	Normal	Corrections to two regression tests	Jeremy Bennett	08/25/2012 04:05 pm
	552	Patch	Closed	Normal	Tidy up .gitignore and MANIFEST.SKIP	Jeremy Bennett	08/25/2012 11:52 am
	536	Issue	Closed	Normal	Regression test driver does not generate initial VCD values	Jeremy Bennett	07/24/2012 10:49 pm
	535	Issue	NoFixNeeded	Low	SystemC 2.3.0 does not work with Verilator tests		11/03/2012 12:08 pm

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