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Issues

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	#	Tracker	Status	Priority	Subject	Assignee	Updated
	638	Patch	Closed	Normal	Support for sc_uint, sc_biguint	Alex Hornung	05/11/2013 08:17 pm
	628	Issue	Closed	Low	SystemVerilog support enhancement request (vector width coercion)	Wilson Snyder	03/09/2013 09:51 pm
	625	Issue	Duplicate	Normal	Verilator does not support expressions in LHS of condition in generate for loop.		02/22/2013 10:01 pm
	624	Issue	Closed	Normal	$fopen("file") should have an implicit mode of "w"		03/09/2013 09:52 pm
	623	Issue	WillNotFix	Normal	Non-single bit wide signal pos/negedge sensitivity		02/23/2013 02:40 am
	618	Issue	Closed	Low	SystemVerilog support enhancement request (structure literals)	Wilson Snyder	03/09/2013 09:51 pm
	617	Issue	Closed	Normal	SystemVerilog support assignment patters under FUNCREFs	Wilson Snyder	03/09/2013 09:51 pm
	616	Issue	Closed	Normal	SystemVerilog support pattern assignment to CONSTDTYPEs	Wilson Snyder	03/09/2013 09:51 pm
	613	Issue	Feature	Normal	Better gated clock support		04/09/2013 02:53 pm
	608	Issue	Closed	Normal	SystemVerilog 'wire logic' not supported	Wilson Snyder	02/05/2013 03:21 am
	605	Issue	Closed	Normal	bit-select with :+ and :- fails with packed structures	Jeremy Bennett	01/18/2013 02:49 am
	603	Issue	Closed	Normal	Bit select from 1-bit parameter causes error	Wilson Snyder	02/05/2013 03:22 am
	602	Issue	Closed	High	SystemVerilog bind support	Wilson Snyder	02/15/2013 01:48 pm
	600	Issue	Closed	Normal	Bit selection from struct causes internal error	Wilson Snyder	02/05/2013 03:21 am
	592	Issue	Closed	Low	Support for export in package declarations		01/01/2013 02:19 pm
	588	Patch	Closed	Normal	Add more vpi features	Rich Porter	02/08/2013 11:10 pm
	586	Issue	Closed	Normal	Use of package qualified parameters	Wilson Snyder	01/10/2013 03:26 am
	578	Patch	NoFixNeeded	Normal	Short-circuit bitwise-AND and bitwise-OR (Verilog only)	Jeremy Bennett	11/14/2012 02:30 am
	570	Patch	Closed	Normal	Triggering initial edge from X	Jeremy Bennett	11/04/2012 12:25 am
	566	Issue	Closed	Normal	Referencing SystemVerilog struct field of a member of an array of structs	Wilson Snyder	11/04/2012 12:25 am
	546	Issue	Assigned	Normal	Support static inside task		08/10/2012 11:42 pm
	545	Issue	Feature	Normal	Support queues		08/09/2012 01:58 am
	544	Issue	Feature	Normal	Support associative arrays		08/10/2012 11:57 pm
	532	Issue	Closed	Normal	Support +systemverilogext+	Jeremy Bennett	12/01/2012 09:41 pm
	528	Issue	Feature	Normal	Support for reserved words weak0 and weak1		11/03/2012 12:04 pm

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