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Issues

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	#	Tracker	Status	Priority	Subject	Assignee	Updated
	629	Issue	Feature	Low	Non-vector timing loop warning		03/16/2013 12:33 am
	593	Issue	Feature	Low	Support running make and creating top C file		01/15/2013 12:20 pm
	533	Issue	Assigned	Low	Missing width warning when part of a bus is compared		07/20/2012 03:27 pm
	509	Issue	Assigned	Low	Better error when illegal bit select of array		05/10/2012 07:14 am
	496	Issue	Feature	Low	Unsupported: tristate construct: ASSIGNDLY		04/26/2012 11:14 pm
	493	Issue	Feature	Low	suppress useless width warning on string parameter comparisons		04/26/2012 08:24 pm
	485	Issue	Feature	Low	verilator does not detect if block name is used twice		04/19/2012 09:46 pm
	476	Issue	Feature	Low	Support && inside sensitivity list		04/03/2012 10:15 pm
	468	Issue	Feature	Low	Support primitive instantiations		04/25/2012 12:43 am
	467	Issue	Feature	Low	Support old format $display ($time, "...")		04/24/2012 07:21 pm
	408	Issue	Assigned	Low	verilator generates incorrect C++ code when genvar is used incorrectly		03/10/2012 07:09 am
	385	Issue	Feature	Low	Dpi exported tasks with array inputs don't compile.	Wilson Snyder	07/15/2012 03:19 pm
	364	Issue	Assigned	Low	blocking & non-blocking assigns -- verilator issues error when no logical conflict exists	Wilson Snyder	04/15/2012 08:28 pm
	285	Issue	Feature	Low	Verilator lint misses bogusly-typed assignment and generates invalid C++	Wilson Snyder	09/26/2010 11:15 am
	652	Issue	Resolved	Normal	Width mismatch problem	Wilson Snyder	05/25/2013 01:30 am
	651	Issue	Resolved	Normal	Different versions of GCC cause Verilator generated models to succeed or fail	Jeremy Bennett	05/24/2013 12:21 am
	649	Issue	Feature	Normal	support for streaming operators		05/22/2013 12:31 am
	648	Issue	Assigned	Normal	Error-BLKANDNBLK with nested modules in generate block		05/22/2013 02:41 am
	646	Issue	AskedReporter	Normal	Asignments of arithmetic operations embedded in a concatenation cause wrong conditional paths to be taken		05/19/2013 02:00 pm
	645	Issue	Resolved	Normal	VL_INW and VL_OUTW macros require 4 arguments, but only 3 given	Wilson Snyder	05/21/2013 11:52 pm
	622	Issue	AskedReporter	Normal	Public signal driven by C++ not propagating as expected		02/23/2013 08:36 pm
	621	Issue	Feature	Normal	Enable duplicate gate elimination in ~3.848.		02/21/2013 01:18 am
	620	Issue	Assigned	Normal	Comparison against x and z leads to verilator crash	Wilson Snyder	02/21/2013 11:50 am
	613	Issue	Feature	Normal	Better gated clock support		04/09/2013 02:53 pm
	576	Issue	Feature	Normal	generate/endgenerate should not be optional in Verilog 2001		11/14/2012 01:38 am

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