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Issues

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	#	Tracker	Status	Priority	Subject	Assignee	Updated
	378	Issue	Feature	Normal	Support properties and assertions		03/02/2012 11:42 pm
	421	Issue	Feature	Normal	Add an option for a custom header comment	Jeremy Bennett	11/17/2011 09:02 am
	380	Issue	Feature	Normal	Support of VHDL93	Sebastien Van Cauwenberghe	08/10/2011 06:49 am
	337	Issue	Feature	Normal	Compile Issue with Large Design with Large I/O Buswidth	Wilson Snyder	03/30/2011 11:22 am
	63	Issue	Feature	Normal	False Signal unoptimizable: circular logic warning		10/25/2010 08:07 pm
	285	Issue	Feature	Low	Verilator lint misses bogusly-typed assignment and generates invalid C++	Wilson Snyder	09/26/2010 11:15 am
	234	Issue	Feature	Normal	Support time and `timescales		04/07/2010 01:27 pm
	235	Issue	Feature	Normal	Support fork-joins and time delays		04/07/2010 01:27 pm
	236	Issue	Feature	Normal	Support real event loop		04/07/2010 01:26 pm
	225	Issue	Feature	Normal	hierarchical compilation of designs for scalability		03/17/2010 08:14 pm
	102	Issue	Feature	Normal	Support "interface" and "endinterface" keywords	Byron Bradley	02/04/2010 11:16 am
	207	Issue	Feature	Normal	Support assignment between packed arrays with different dimensions	Byron Bradley	01/19/2010 08:43 pm
	50	Issue	Feature	Normal	Clock gating support?		10/28/2009 01:51 pm
	646	Issue	AskedReporter	Normal	Asignments of arithmetic operations embedded in a concatenation cause wrong conditional paths to be taken		05/19/2013 02:00 pm
	622	Issue	AskedReporter	Normal	Public signal driven by C++ not propagating as expected		02/23/2013 08:36 pm
	648	Issue	Assigned	Normal	Error-BLKANDNBLK with nested modules in generate block		05/22/2013 02:41 am
	620	Issue	Assigned	Normal	Comparison against x and z leads to verilator crash	Wilson Snyder	02/21/2013 11:50 am
	487	Issue	Assigned	Normal	Support short-circuiting of bitswise AND and OR	Jeremy Bennett	11/14/2012 08:06 pm
	546	Issue	Assigned	Normal	Support static inside task		08/10/2012 11:42 pm
	533	Issue	Assigned	Low	Missing width warning when part of a bus is compared		07/20/2012 03:27 pm
	509	Issue	Assigned	Low	Better error when illegal bit select of array		05/10/2012 07:14 am
	364	Issue	Assigned	Low	blocking & non-blocking assigns -- verilator issues error when no logical conflict exists	Wilson Snyder	04/15/2012 08:28 pm
	408	Issue	Assigned	Low	verilator generates incorrect C++ code when genvar is used incorrectly		03/10/2012 07:09 am
	449	Issue	Assigned	Normal	Using public accessor tasks/functions to read and write registers causes BLKANDNBLK error	Wilson Snyder	03/07/2012 02:09 pm
	365	Issue	Assigned	Normal	bidrectional arrays not supported as module ports		07/21/2011 11:33 am

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