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Issues

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Issues

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	#	Tracker	Status	Priority	Subject	Assignee	Updated
	655	Issue	Resolved	Normal	vpi memory iterator	Rich Porter	06/17/2013 08:29 pm
	613	Issue	Resolved	Normal	Better gated clock support	Jeremy Bennett	06/06/2013 03:38 am
	653	Issue	Assigned	Normal	vcddiff tests fail with latest gpl-cver vcddiff	Wilson Snyder	05/30/2013 09:57 pm
	648	Issue	Assigned	Normal	Error-BLKANDNBLK with nested modules in generate block		05/22/2013 02:41 am
	620	Issue	Assigned	Normal	Comparison against x and z leads to verilator crash	Wilson Snyder	02/21/2013 11:50 am
	546	Issue	Assigned	Normal	Support static inside task		08/10/2012 11:42 pm
	533	Issue	Assigned	Low	Missing width warning when part of a bus is compared		07/20/2012 03:27 pm
	509	Issue	Assigned	Low	Better error when illegal bit select of array		05/10/2012 07:14 am
	487	Issue	Assigned	Normal	Support short-circuiting of bitswise AND and OR	Jeremy Bennett	11/14/2012 08:06 pm
	449	Issue	Assigned	Normal	Using public accessor tasks/functions to read and write registers causes BLKANDNBLK error	Wilson Snyder	03/07/2012 02:09 pm
	408	Issue	Assigned	Low	verilator generates incorrect C++ code when genvar is used incorrectly		03/10/2012 07:09 am
	366	Issue	Assigned	Normal	Unsupported sensitivity of arrayed variables		07/21/2011 11:31 am
	365	Issue	Assigned	Normal	bidrectional arrays not supported as module ports		07/21/2011 11:33 am
	364	Issue	Assigned	Low	blocking & non-blocking assigns -- verilator issues error when no logical conflict exists	Wilson Snyder	04/15/2012 08:28 pm
	646	Issue	AskedReporter	Normal	Asignments of arithmetic operations embedded in a concatenation cause wrong conditional paths to be taken		05/19/2013 02:00 pm
	622	Issue	AskedReporter	Normal	Public signal driven by C++ not propagating as expected		02/23/2013 08:36 pm
	649	Issue	Feature	Normal	support for streaming operators		05/22/2013 12:31 am
	629	Issue	Feature	Low	Non-vector timing loop warning		03/16/2013 12:33 am
	593	Issue	Feature	Low	Support running make and creating top C file		01/15/2013 12:20 pm
	576	Issue	Feature	Normal	generate/endgenerate should not be optional in Verilog 2001		11/14/2012 01:38 am
	545	Issue	Feature	Normal	Support queues		08/09/2012 01:58 am
	544	Issue	Feature	Normal	Support associative arrays		08/10/2012 11:57 pm
	528	Issue	Feature	Normal	Support for reserved words weak0 and weak1		11/03/2012 12:04 pm
	517	Issue	Feature	Normal	Constant expression in generated block index not recognized		10/08/2012 04:11 pm
	506	Issue	Feature	Normal	Support SystemVerilog string initializations		05/05/2012 03:39 pm
	496	Issue	Feature	Low	Unsupported: tristate construct: ASSIGNDLY		04/26/2012 11:14 pm
	493	Issue	Feature	Low	suppress useless width warning on string parameter comparisons		04/26/2012 08:24 pm
	485	Issue	Feature	Low	verilator does not detect if block name is used twice		04/19/2012 09:46 pm
	476	Issue	Feature	Low	Support && inside sensitivity list		04/03/2012 10:15 pm
	468	Issue	Feature	Low	Support primitive instantiations		04/25/2012 12:43 am
	467	Issue	Feature	Low	Support old format $display ($time, "...")		04/24/2012 07:21 pm
	466	Issue	Feature	Normal	Support wires with array declarations		03/23/2012 12:51 pm
	460	Issue	Feature	Normal	Support enumeration type methods		03/21/2012 12:38 am
	421	Issue	Feature	Normal	Add an option for a custom header comment	Jeremy Bennett	11/17/2011 09:02 am
	392	Issue	Feature	Normal	Can't unroll generate for with complicated incrementer/init/test	Wilson Snyder	02/22/2013 10:01 pm
	385	Issue	Feature	Low	Dpi exported tasks with array inputs don't compile.	Wilson Snyder	07/15/2012 03:19 pm
	380	Issue	Feature	Normal	Support of VHDL93	Sebastien Van Cauwenberghe	08/10/2011 06:49 am
	379	Issue	Feature	Normal	Support dynamic memory new and delete		03/02/2012 11:42 pm
	378	Issue	Feature	Normal	Support properties and assertions		03/02/2012 11:42 pm
	377	Issue	Feature	Normal	Support classes and methods		03/02/2012 11:42 pm
	376	Issue	Feature	Normal	Support "parameter type"		04/08/2012 10:02 pm
	355	Issue	Feature	Normal	Support '{...}		08/12/2012 07:14 pm
	337	Issue	Feature	Normal	Compile Issue with Large Design with Large I/O Buswidth	Wilson Snyder	03/30/2011 11:22 am
	285	Issue	Feature	Low	Verilator lint misses bogusly-typed assignment and generates invalid C++	Wilson Snyder	09/26/2010 11:15 am
	236	Issue	Feature	Normal	Support real event loop		04/07/2010 01:26 pm
	235	Issue	Feature	Normal	Support fork-joins and time delays		04/07/2010 01:27 pm
	234	Issue	Feature	Normal	Support time and `timescales		04/07/2010 01:27 pm
	225	Issue	Feature	Normal	hierarchical compilation of designs for scalability		03/17/2010 08:14 pm
	207	Issue	Feature	Normal	Support assignment between packed arrays with different dimensions	Byron Bradley	01/19/2010 08:43 pm
	63	Issue	Feature	Normal	False Signal unoptimizable: circular logic warning		10/25/2010 08:07 pm
	50	Issue	Feature	Normal	Clock gating support?		10/28/2009 01:51 pm
	658	Issue	New	Normal	SystemVerilog interfaces: Internal error when connecting interfaces		06/18/2013 04:37 pm
	657	Issue	New	Normal	Read Parmetarized Verilog File		06/18/2013 07:01 pm

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