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Issues

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	#	Tracker	Status	Priority	Subject	Assignee	Updated
	50	Issue	Feature	Normal	Clock gating support?		10/28/2009 01:51 pm
	63	Issue	Feature	Normal	False Signal unoptimizable: circular logic warning		10/25/2010 08:07 pm
	225	Issue	Feature	Normal	hierarchical compilation of designs for scalability		03/17/2010 08:14 pm
	234	Issue	Feature	Normal	Support time and `timescales		04/07/2010 01:27 pm
	235	Issue	Feature	Normal	Support fork-joins and time delays		04/07/2010 01:27 pm
	236	Issue	Feature	Normal	Support real event loop		04/07/2010 01:26 pm
	355	Issue	Feature	Normal	Support '{...}		08/12/2012 07:14 pm
	376	Issue	Feature	Normal	Support "parameter type"		04/08/2012 10:02 pm
	377	Issue	Feature	Normal	Support classes and methods		03/02/2012 11:42 pm
	378	Issue	Feature	Normal	Support properties and assertions		03/02/2012 11:42 pm
	379	Issue	Feature	Normal	Support dynamic memory new and delete		03/02/2012 11:42 pm
	460	Issue	Feature	Normal	Support enumeration type methods		03/21/2012 12:38 am
	466	Issue	Feature	Normal	Support wires with array declarations		03/23/2012 12:51 pm
	506	Issue	Feature	Normal	Support SystemVerilog string initializations		05/05/2012 03:39 pm
	517	Issue	Feature	Normal	Constant expression in generated block index not recognized		10/08/2012 04:11 pm
	528	Issue	Feature	Normal	Support for reserved words weak0 and weak1		11/03/2012 12:04 pm
	544	Issue	Feature	Normal	Support associative arrays		08/10/2012 11:57 pm
	545	Issue	Feature	Normal	Support queues		08/09/2012 01:58 am
	576	Issue	Feature	Normal	generate/endgenerate should not be optional in Verilog 2001		11/14/2012 01:38 am
	613	Issue	Feature	Normal	Better gated clock support		04/09/2013 02:53 pm
	621	Issue	Feature	Normal	Enable duplicate gate elimination in ~3.848.		02/21/2013 01:18 am
	467	Issue	Feature	Low	Support old format $display ($time, "...")		04/24/2012 07:21 pm
	468	Issue	Feature	Low	Support primitive instantiations		04/25/2012 12:43 am
	476	Issue	Feature	Low	Support && inside sensitivity list		04/03/2012 10:15 pm
	485	Issue	Feature	Low	verilator does not detect if block name is used twice		04/19/2012 09:46 pm

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