Activity
From 01/07/2012 to 02/05/2012
Today
- 02:35 am Issue #386: Indenting of user-defined data types
- BTW verilog-typedef-regexp if used needs to be specified as "\\w+_s\\>" or similar, since it needs to match in the mi...
- 02:32 am Issue #386: Indenting of user-defined data types
- I searched for "int" in verilog-mode.el and followed verilog-declaration-core-re to verilog-declaration-re. Adding t...
02/03/2012
- 02:38 pm Issue #437 (New): Indentation of continued assignment incorrect if first line ends with ']'
- The indentation of an expression continued over multiple lines is incorrect when the first line of the expression end...
02/02/2012
- 09:07 pm Issue #435: Indenting comments on declarations in v736
- Wilson,
Thanks for the quick reply, but in creating the test case I think I confused the issue. I am not concerne... - 08:46 pm Issue #435: Indenting comments on declarations in v736
- There's really two things here.
The first is the space between "input" and the signal name. This was changed in r... - 08:14 pm Issue #435 (New): Indenting comments on declarations in v736
- I don't know when this stopped working, but in v736, comments on declaration lines no longer use comment-column:
<...
01/27/2012
- 10:52 pm Issue #433: indenting for some forms of SystemVerilog constraints is wrong/odd
- wow. the html (or php?) code "displayer" really mangled that code. That's not at all what I pasted.
I'll try and... - 10:50 pm Issue #433 (New): indenting for some forms of SystemVerilog constraints is wrong/odd
- indentation for several different forms of SV constraints is wrong or odd;
specifically, empty constraints are odd, ...
01/12/2012
- 04:31 pm Patch #429 (Closed): Remove interfaced ports from auto-inst of interfaces
- I added 'verilog-auto-inst-interfaced-ports' with the opposite sense (to avoid the negation in the definition) to r77...
01/10/2012
- 12:45 pm Issue #430: Incorrect indentation in Verilog Mode v736
- Here's another fragment that shows a similar issue, probably the same bug:...
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