Verilog-mode - Issues

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#	Tracker	Status	Priority	Subject	Assigned to	Updated
218	Issue	New	Normal	pure virtual indentation	Michael McNamara	02/19/2010 02:04 pm
203	Patch	Assigned	Normal	Verilog-mode support for the `elsif directive	Michael McNamara	01/13/2010 11:44 am
195	Issue	Resolved	Normal	AUTOWIRE does not work with types declared in a package (SystemVerilog)	Wilson Snyder	12/10/2009 02:00 pm
190	Issue	Assigned	Normal	verilog-mode tab indention different before and after always block	Michael McNamara	12/10/2009 11:48 am
105	Issue	Assigned	Normal	verilog-mode 528: Improper indentation of assert property and subsequent statements	Michael McNamara	12/10/2009 11:49 am
95	Issue	Assigned	Normal	Attributes indent incorrectly	Michael McNamara	06/04/2009 05:21 pm

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