[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  Schedule::Load
  SVN::S4
  Synopsys-modes
  SystemPerl
  Verilog-Pli
  Voneline
  Vregs
General Info
  Papers

Issues

If you wish to add a new issue, you must log in and create an account; "New Issue" will then appear in the menu bar. Sorry, but this was necessary to prevent form-filling spam.
Filters

Apply Clear

Toggle_check # Tracker Status Priority Subject Assignee Updated
437 IssueNewNormalIndentation of continued assignment incorrect if first line ends with ']'02/03/2012 02:38 pm
435 IssueNewNormalIndenting comments on declarations in v73602/02/2012 09:07 pm
433 IssueNewNormalindenting for some forms of SystemVerilog constraints is wrong/odd01/27/2012 10:52 pm
430 IssueNewNormalIncorrect indentation in Verilog Mode v736Michael McNamara01/10/2012 12:45 pm
427 IssueNewNormalalignment in always @(*) blocks behaves strangelyMichael McNamara01/02/2012 05:05 pm
399 IssueResolvedNormalalignment of assignment operators and comparison operatorsMichael McNamara12/15/2011 06:46 pm
386 IssueNewNormalIndenting of user-defined data types02/05/2012 02:35 am
372 IssueFeatureLowFeature request - add syntax highlighting to C pre-processor directivesMichael McNamara08/25/2011 08:52 pm
336 IssueAssignedNormalIncredibly slow IndentingMichael McNamara04/12/2011 07:28 pm
332 IssueNewNormalCalculated parameters in port widthsWilson Snyder03/09/2011 06:41 pm
330 IssueNewNormalIdentation after always* construct inside named blockMichael McNamara03/09/2011 02:59 am
324 IssueAssignedNormalverilog-mode constraint indentation is not correctMichael McNamara02/04/2011 01:52 pm
320 IssueAssignedNormalInterface port connection using .* is wrong (?)Wilson Snyder01/27/2011 09:56 pm
308 IssueFeatureNormalIndenting/Highlighting user defined typesMichael McNamara02/21/2011 02:21 am
290 IssueResolvedNormalIndentation wrong after import "DPI-C"Michael McNamara12/15/2011 06:47 pm
286 IssueNewLowIdentation of classes inside package in SystemVerilogMichael McNamara09/27/2010 07:41 am
279 IssueAssignedNormalSystemVerilog Constraint auto-indentationMichael McNamara12/02/2010 02:53 pm
271 IssueNewNormalIndentation issues with doxygen commentsMichael McNamara08/18/2010 02:20 pm
104 IssueFeedbackNormalIndentation failures in v528Michael McNamara12/15/2011 06:50 pm

(1-19/19) | Per page: 25, 100, 250

Also available in: Atom CSV