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Issues

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Toggle_check # Tracker Status Priority Subject Assignee Updated
353 IssueClosedNormalAUTOARG and SV typedef as portWilson Snyder05/17/2011 10:55 am
340 IssueClosedNormalparameter type not included in AUTOINSTPARAMWilson Snyder11/29/2011 03:01 pm
338 IssueClosedNormalAUTOLOGIC and AUTOBITWilson Snyder04/12/2011 07:27 pm
332 IssueNewNormalCalculated parameters in port widthsWilson Snyder05/31/2012 01:51 pm
331 IssueClosedNormalUsing {@"vl-width"{1'b0}} in auto_template on a parameterized width inputWilson Snyder04/12/2011 07:52 pm
330 IssueNewNormalIdentation after always* construct inside named blockMichael McNamara03/09/2011 02:59 am
325 IssueClosedLowverilog-mode infinite loops with malformed inputWilson Snyder02/22/2011 02:35 pm
322 IssueClosedNormalMultiple RegEx matches in Instance Name as part of AUTO_TEMPLATEWilson Snyder11/29/2011 02:14 pm
320 IssueAssignedNormalInterface port connection using .* is wrong (?)Wilson Snyder01/27/2011 09:56 pm
317 IssueClosedNormalAUTOWIRE does not support package_import_declaration before module port listWilson Snyder01/19/2011 05:41 pm
313 IssueClosedNormalUsing verilog-mode with .v and .sv filesWilson Snyder01/13/2011 11:18 pm
303 IssueClosedNormalCouldn't merge the signals with * in bit positions. Ex [224*1-1:128*1]Wilson Snyder12/03/2010 09:41 pm
302 IssueClosedNormalAUTOINST and AUTOINSTPARAM problemWilson Snyder11/30/2010 09:54 am
295 IssueClosedNormalAUTOWIRE does not declare wire for AUTOINST output when interface has same nameWilson Snyder10/20/2010 02:04 pm
294 IssueClosedNormalAUTOS does not support array of signalsWilson Snyder10/22/2010 02:40 am
293 IssueClosedNormalverilog-mode /*AUTOINPUT*/ 2001 styleWilson Snyder01/19/2011 05:43 pm
287 IssueClosedNormalProblem with AUTOINST and AUTOINSTPARAM wrt parameter valueWilson Snyder09/27/2010 03:24 pm
284 IssueClosedNormalFeature Request: Support For Verilog Primitive GatesWilson Snyder10/05/2010 08:35 pm
281 IssueClosedNormalUser-defined SystemVerilog ports pick up datatype as portnameWilson Snyder09/10/2010 05:05 pm
270 IssueClosedNormalAUTOINST and SystemVerilog interfacesWilson Snyder08/18/2010 02:19 pm
269 PatchClosedNormalA patch to add verilog-auto-tieoff-ignore-regexpWilson Snyder07/15/2010 11:08 am
259 IssueClosedNormalWrong insertion of AUTOARG in TaskWilson Snyder08/18/2010 02:20 pm
250 IssueClosedNormal%Error: Stack overflow in regexp matcher Wilson Snyder04/30/2010 01:27 pm
245 IssueClosedNormal.PORT System Verilog autoinst namingWilson Snyder04/20/2010 02:40 pm
195 IssueClosedNormalAUTOWIRE does not work with types declared in a package (SystemVerilog)Wilson Snyder04/20/2010 02:40 pm

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