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Issues

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Toggle_check # Tracker Status Priority Subject Assignee Updated
640 IssueWillNotFixNormalAUTOINST truncates inputs with array instantiation and wide inputs05/01/2013 05:23 pm
637 IssueClosedNormalArray ports are not handled properly by AUTOINSTWilson Snyder04/30/2013 12:57 pm
612 IssueClosedHighconfused using AUTO_TEMPLATE with regexp for instance name and pin nameWilson Snyder02/04/2013 07:32 pm
597 IssueAssignedNormalProblem with verilog-typedef-regexpWilson Snyder12/31/2012 01:35 pm
594 IssueClosedHighBug report: macro parsing hangWilson Snyder12/21/2012 03:12 pm
590 IssueClosedNormalAUTORESET improperly tries to initialize arrays12/17/2012 04:06 pm
565 IssueClosedNormalAdding parameters to module causes first interface to disappear in AUTOINSTWilson Snyder10/08/2012 09:19 pm
558 IssueClosedNormalRegular Expression Grouping in AUTOINOUTMODULE functionsWilson Snyder09/06/2012 01:23 pm
540 IssueClosedNormalAUTOINSTing an interface create illegal codeWilson Snyder08/21/2012 12:27 am
539 IssueClosedHighAUTOs for wrapping a module around an interfaceWilson Snyder08/19/2012 11:33 pm
529 PatchClosedNormalAdd batch mode for verilog-delete-trailing-whitespaceWilson Snyder07/15/2012 03:44 pm
522 IssueClosedNormalExpand $clog2 in AUTOINST param port widthsWilson Snyder05/31/2012 03:23 pm
445 IssueClosedNormalAUTOINST uses the wrong AUTO_TEMPLATEWilson Snyder02/29/2012 12:50 pm
438 IssueClosedNormalsupply1, supply0 variables get wrongly autoexpanded as input ports with /*AUTOREG*/Wilson Snyder02/13/2012 01:26 pm
429 PatchClosedNormalRemove interfaced ports from auto-inst of interfacesWilson Snyder01/12/2012 04:31 pm
411 IssueClosedNormalStrange behavior with AUTOINPUT/AUTOOUTPUTWilson Snyder11/29/2011 02:01 pm
383 IssueClosedNormalCommented Instantiation text kills AUTOINSTWilson Snyder08/24/2011 06:44 pm
381 IssueClosedNormalAUTORESET adds resets for variables that are out of scopeWilson Snyder09/13/2011 02:17 pm
375 IssueClosedNormalrepeated invocations of verilog-auto produce different resultsWilson Snyder11/29/2011 02:02 pm
373 IssueClosedNormalAUTO problems with ports of type array of structuresWilson Snyder08/09/2011 11:32 pm
371 IssueClosedNormalAdd variable to automatically "delete-trailing-whitespace" after updating AUTOsWilson Snyder07/21/2011 02:22 pm
360 IssueClosedLowOpening comment inside string breaks verilog-modeWilson Snyder06/28/2011 04:11 pm
358 IssueClosedNormalverilog-auto-inst variable to control sorting ports in AUTOINSTWilson Snyder06/17/2011 03:28 pm
357 IssueClosedNormalverilog-auto-inst variable to print matching AUTO_TEMPLATE ruleWilson Snyder06/17/2011 02:39 pm
356 IssueClosedNormalAUTO_LISP not evaluating correctlyWilson Snyder11/29/2011 02:18 pm
353 IssueClosedNormalAUTOARG and SV typedef as portWilson Snyder05/17/2011 10:55 am
340 IssueClosedNormalparameter type not included in AUTOINSTPARAMWilson Snyder11/29/2011 03:01 pm
338 IssueClosedNormalAUTOLOGIC and AUTOBITWilson Snyder04/12/2011 07:27 pm
332 IssueNewNormalCalculated parameters in port widthsWilson Snyder05/31/2012 01:51 pm
331 IssueClosedNormalUsing {@"vl-width"{1'b0}} in auto_template on a parameterized width inputWilson Snyder04/12/2011 07:52 pm
330 IssueNewNormalIdentation after always* construct inside named blockMichael McNamara03/09/2011 02:59 am
325 IssueClosedLowverilog-mode infinite loops with malformed inputWilson Snyder02/22/2011 02:35 pm
322 IssueClosedNormalMultiple RegEx matches in Instance Name as part of AUTO_TEMPLATEWilson Snyder11/29/2011 02:14 pm
320 IssueAssignedNormalInterface port connection using .* is wrong (?)Wilson Snyder01/27/2011 09:56 pm
317 IssueClosedNormalAUTOWIRE does not support package_import_declaration before module port listWilson Snyder01/19/2011 05:41 pm
313 IssueClosedNormalUsing verilog-mode with .v and .sv filesWilson Snyder01/13/2011 11:18 pm
303 IssueClosedNormalCouldn't merge the signals with * in bit positions. Ex [224*1-1:128*1]Wilson Snyder12/03/2010 09:41 pm
302 IssueClosedNormalAUTOINST and AUTOINSTPARAM problemWilson Snyder11/30/2010 09:54 am
295 IssueClosedNormalAUTOWIRE does not declare wire for AUTOINST output when interface has same nameWilson Snyder10/20/2010 02:04 pm
294 IssueClosedNormalAUTOS does not support array of signalsWilson Snyder10/22/2010 02:40 am
293 IssueClosedNormalverilog-mode /*AUTOINPUT*/ 2001 styleWilson Snyder01/19/2011 05:43 pm
287 IssueClosedNormalProblem with AUTOINST and AUTOINSTPARAM wrt parameter valueWilson Snyder09/27/2010 03:24 pm
284 IssueClosedNormalFeature Request: Support For Verilog Primitive GatesWilson Snyder10/05/2010 08:35 pm
281 IssueClosedNormalUser-defined SystemVerilog ports pick up datatype as portnameWilson Snyder09/10/2010 05:05 pm
270 IssueClosedNormalAUTOINST and SystemVerilog interfacesWilson Snyder08/18/2010 02:19 pm
269 PatchClosedNormalA patch to add verilog-auto-tieoff-ignore-regexpWilson Snyder07/15/2010 11:08 am
259 IssueClosedNormalWrong insertion of AUTOARG in TaskWilson Snyder08/18/2010 02:20 pm
250 IssueClosedNormal%Error: Stack overflow in regexp matcher Wilson Snyder04/30/2010 01:27 pm
245 IssueClosedNormal.PORT System Verilog autoinst namingWilson Snyder04/20/2010 02:40 pm
195 IssueClosedNormalAUTOWIRE does not work with types declared in a package (SystemVerilog)Wilson Snyder04/20/2010 02:40 pm
82 IssueClosedNormalComma Incorrectly DeletesWilson Snyder05/04/2009 08:02 pm
75 IssueClosedNormalsupport SV instances in port list with AUTOsWilson Snyder12/10/2009 11:47 am
74 IssueWillNotFixLow/*AUTOWIRE*/ of undriven inputsWilson Snyder04/02/2009 09:45 pm

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