Home
News
Activity
About/Contact
Major Tools
Dinotrace
Verilator
Verilog-mode
Verilog-Perl
Other Tools
BugVise
CovVise
Gspice
IPC::Locker
Rsvn
Schedule::Load
SVN::S4
Synopsys-modes
SystemPerl
Verilog-Pli
Voneline
Vregs
General Info
Book Tips
Papers
Sign in
Register
Search
:
Verilog-mode
Intro
Download
Examples
Faq
Docs
Activity
News
Issues
Wiki
Forums
Issues
View all issues
Summary
Issues
If you wish to add a new issue, you must log in and create an account; "New Issue" will then appear in the menu bar. Sorry, but this was necessary to prevent form-filling spam.
Filters
Status
open
is
is not
closed
all
New
Feature
AskedReporter
Assigned
Resolved
Feedback
Closed
Rejected
Tracker
is
is not
Issue
Patch
Priority
is
is not
Low
Normal
High
Urgent
Assigned to
is
is not
none
all
Auto Update Daemon
Michael McNamara
Wilson Snyder
Author
is
is not
Auto Update Daemon
Michael McNamara
Wilson Snyder
Category
is
is not
none
all
Autos
Documentation
General
Highlighting
Indents
Subject
contains
doesn't contain
Created
less than days ago
more than days ago
days ago
today
this week
days
Updated
less than days ago
more than days ago
days ago
today
this week
days
Start
in less than
in more than
in
today
this week
less than days ago
more than days ago
days ago
days
Due date
in less than
in more than
in
today
this week
less than days ago
more than days ago
days ago
days
Estimated time
is
>=
<=
none
all
% Done
is
>=
<=
none
all
Add filter
:
Tracker
Priority
Assigned to
Author
Category
Subject
Created
Updated
Start
Due date
Estimated time
% Done
Options
Columns
Project
Parent task
Author
Category
Target version
Start
Due date
Estimated time
% Done
Created
Tracker
Status
Priority
Subject
Assigned to
Updated
Group results by
Project
Tracker
Status
Priority
Assigned to
Category
Target version
% Done
Apply
Clear
#
Tracker
Status
Priority
Subject
Assigned to
Updated
279
Issue
New
Normal
SystemVerilog Constraint auto-indentation
08/18/2010 11:49 pm
260
Issue
New
Normal
Feature Request: Autoformat/indent Verilog 2001 Module Headers
Michael McNamara
08/18/2010 02:21 pm
271
Issue
New
Normal
Indentation issues with doxygen comments
Michael McNamara
08/18/2010 02:20 pm
273
Issue
New
Normal
Verilog-mode module parameter indentation
Michael McNamara
07/28/2010 04:08 am
104
Issue
Assigned
Normal
Indentation failures in v528
Michael McNamara
06/29/2010 12:20 pm
(1-5/5) | Per page:
25
,
100
, 250
Also available in:
Atom
CSV
PDF
Loading...