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Issues

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Status open is is not closed all New Feature AskedReporter Assigned Resolved Feedback Closed Rejected Tracker is is not Issue Patch Priority is is not Low Normal High Urgent Assigned to is is not none all Auto Update Daemon Michael McNamara Wilson Snyder Author is is not Auto Update Daemon Michael McNamara Wilson Snyder Category is is not none all Autos Documentation General Highlighting Indents Subject contains doesn't contain Created less than days ago more than days ago days ago today this week days Updated less than days ago more than days ago days ago today this week days Start in less than in more than in today this week less than days ago more than days ago days ago days Due date in less than in more than in today this week less than days ago more than days ago days ago days Estimated time is >= <= none all % Done is >= <= none all

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Columns	Project Parent task Author Category Target version Start Due date Estimated time % Done Created Tracker Status Priority Subject Assigned to Updated
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	#	Tracker	Status	Priority	Subject	Assigned to	Updated
	279	Issue	New	Normal	SystemVerilog Constraint auto-indentation		08/18/2010 11:49 pm
	260	Issue	New	Normal	Feature Request: Autoformat/indent Verilog 2001 Module Headers	Michael McNamara	08/18/2010 02:21 pm
	271	Issue	New	Normal	Indentation issues with doxygen comments	Michael McNamara	08/18/2010 02:20 pm
	273	Issue	New	Normal	Verilog-mode module parameter indentation	Michael McNamara	07/28/2010 04:08 am
	104	Issue	Assigned	Normal	Indentation failures in v528	Michael McNamara	06/29/2010 12:20 pm

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