Verilog-Perl

11/04/2010

10:52 am Issue #300: Macro name == module name interferes with module location via -y

You're right, I added a test, saw it fail, then added the fix.
Wilson Snyder

11/03/2010

11:47 pm Issue #300: Macro name == module name interferes with module location via -y

Thanks for the quick update, but I think the fix will have the same problem. (Disclaimer: I only examined the modifi... John Dickol

05:01 pm Issue #300 (Resolved): Macro name == module name interferes with module location via -y

Should have suspected that one would bite back.
Fixed in git for 3.305+. SystemC users will need the latest Syste... Wilson Snyder

04:29 pm Issue #300 (Closed): Macro name == module name interferes with module location via -y

Some Verilog RTL we received from a vendor (i.e. we can't easily change it) uses an ifdef to control the instantiatio... John Dickol

11:49 am Issue #297 (Resolved): -F enhancement (hierarchical manifests)

In git for 3.305+.
Because Verilog::Getopt just passes through filenames, it won't do what you would
expect if yo... Wilson Snyder

11/02/2010

12:06 am Issue #298 (Resolved): Environment variables not expanded in vhier -f files

Wow, it's amazing I didn't know that getopt issue!
Fixed, and in a bunch of other places too, just to be safe.
... Wilson Snyder

11/01/2010

11:52 pm Issue #298 (Closed): Environment variables not expanded in vhier -f files

Environment variables are not being expanded when I use them in a file read in with -f. The problem appears to be du... John Dickol

10/28/2010

05:32 pm Issue #297 (Closed): -F enhancement (hierarchical manifests)

Enhancement suggestion to add "-F" relative manifest option to augment the existing "-f" method. Allows the use of hi... Neil Hamilton

10/25/2010

09:18 pm Verilog-Perl 3.304 Released

Verilog::Language 3.304 2010/10/25
**** Fix wrong filename on include file errors, bug289. [Brad Parker]
Wilson Snyder