Activity

From 03/04/2012 to 04/02/2012

11:52 pm Issue #471 (Resolved): Parameters outside modules not recognized: This is fixed in git towards 3.315.
Wilson Snyder
10:08 pm Issue #472 (AskedReporter): cc1plus: out of memory allocating for make in Parser: GCC is a memory hog, probably it just needs more than 1GB. If you really don't have more memory than that you can tr... Wilson Snyder
08:46 pm Issue #472 (NoFixNeeded): cc1plus: out of memory allocating for make in Parser: I'm install on cgwin in winxp. gcc version 3.3.3... lionhead wang

11:40 pm Issue #471 (Assigned): Parameters outside modules not recognized: It parses them, just doesn't have a place to put them, as you indicated. I'll make a $root, which is where SystemVer... Wilson Snyder
05:43 pm Issue #471 (Closed): Parameters outside modules not recognized: It seems that "parameter" statements outside of module scope are not recognized by the Verilog-Perl Verilog::Netlist ... Corey Teffetalor

05:02 pm Issue #459 (Resolved): Comment starting line number wrong: Fixed in git towards 3.315.
Wilson Snyder
04:59 pm Issue #459 (Closed): Comment starting line number wrong: The line number that a multiline comment begins at is wrong.
See
http://www.veripool.org/boards/18/topics/show/7... Wilson Snyder

05:58 pm Issue #453: net widths not absolute: Added a FAQ there too.
Wilson Snyder
05:38 pm Issue #453 (WillNotFix): net widths not absolute: What you describe requires elaboration, which is not something Verilog-Perl is intended to do as it requires almost f... Wilson Snyder
05:16 pm Issue #453 (WillNotFix): net widths not absolute: If the net widths are declared as function of some parameters then the widths when accessed with net->width is not ab... Devendra Singh

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