From 04/10/2012 to 05/09/2012
- 12:40 pm Issue #507 (Resolved): assign with value containing newline fails
- 12:35 pm Issue #507 (Assigned): assign with value containing newline fails
- It's the newline, not the spaces.
The parser originally predated Verilog 1995 standard and so needs to see a compl...
- 09:39 am Issue #507 (Closed): assign with value containing newline fails
The verilog parser would fail in case a white space is found after the 'h'
module any_logic ();
- 12:36 pm Issue #256: vhier support of "myreg <= #`FFDLY 'b0;" Verilog notation
- See also bug507 (which was hacked around so now resolved).
- 09:51 pm Issue #472 (NoFixNeeded): cc1plus: out of memory allocating for make in Parser
- 09:51 pm Issue #459 (Closed): Comment starting line number wrong
- In 3.315.
- 09:50 pm Issue #471 (Closed): Parameters outside modules not recognized
- In 3.315.
- 09:50 pm Verilog-Perl 3.315 Released.
- Verilog::Language 3.315 2012/05/04
*** Put root localparams into $root module, bug471. [Corey Teffetalor]
- 01:34 am Issue #504 (AskedReporter): Vrename aborts when parsing a large netlist
- Looks like ~2GB is a Cygwin limitation. A google search suggested http://cygwin.com/cygwin-ug-net/setup-maxmem.html
- 01:17 am Issue #504 (NoFixNeeded): Vrename aborts when parsing a large netlist
- I've a 520MByte Verilog netlist that I'm trying to load using "Vrename --list --xref netlist.v" command.
- 05:08 pm Issue #502 (NoFixNeeded): Verilog::PreProc mistakenly substitute macros in numbers
- Sorry ignore the last mail, I thought you had another define getting substituted in, not the define argument.
- 05:04 pm Issue #502 (NoFixNeeded): Verilog::PreProc mistakenly substitute macros in numbers
- for the following macro definition:...
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