Using - Verilog-Perl

Did anyone ever use the Parser as a stand-alone SV parser in a C++ project?

Jan Seyler

03/21/2012 03:20 pm

42

Added by Jan Seyler 8 days ago
RE: Did anyone ever use the Parser as a stand-alone SV pa...

Does this package work well with SV

Neeraj chandak

03/29/2012 06:21 pm

1

Added by Wilson Snyder about 1 month ago
RE: Does this package work well with SV

Starting line number of star /* comments

Max Bjurling

02/28/2012 09:46 am

2

Added by Wilson Snyder 2 months ago
RE: Starting line number of star /* comments

Possible to ignore verilog directives?

DK Kim

01/18/2012 06:21 pm

5

Ports list in same order as declared?

Salem Boudjelel

11/14/2011 03:12 pm

1

Added by Wilson Snyder 6 months ago
RE: Ports list in same order as declared?

Find fanin and fanout of a pin

Salem Boudjelel

11/08/2011 02:39 pm

3

Added by Wilson Snyder 7 months ago
RE: Find fanin and fanout of a pin

Instant callback returns the last lineno for multiple line instantiation

Jeffrey Lin

10/25/2011 10:22 pm

6

Added by Jeffrey Lin 7 months ago
RE: Instant callback returns the last lineno for multiple...

Use SigParser with non-preprocessed verilog file

Jeffrey Lin

10/25/2011 05:04 pm

2

Added by Jeffrey Lin 7 months ago
RE: Use SigParser with non-preprocessed verilog file

Controlling callback time in Parser.pm

Jeffrey Lin

10/25/2011 01:38 am

2

Added by Jeffrey Lin 7 months ago
RE: Controlling callback time in Parser.pm

Parsing Verilog widths correctly

Ritesh Patel

12/09/2010 07:58 pm

4

Added by Nicky Ayoub 8 months ago
RE: Parsing Verilog widths correctly

vrename help

Jon Stahl

06/16/2011 06:34 pm

1

Added by Wilson Snyder 11 months ago
RE: vrename help

Need some direction

Phillip Prentice

04/26/2011 05:50 pm

1

Added by Wilson Snyder about 1 year ago
RE: Need some direction

error with multiple begin/end in the same generate loop

Mike Z

01/09/2011 04:14 pm

2

Added by Wilson Snyder over 1 year ago
RE: RE: error with multiple begin/end in the same generat...

Trying to understand Verilog::Preroc

Tom Symons

06/27/2009 10:49 pm

1

Added by Gene Sullivan over 1 year ago
RE: Trying to understand Verilog::Preroc

Syntax Errors using Packed Structures

Ritesh Patel

12/09/2010 06:25 pm

2

Added by Ritesh Patel over 1 year ago
RE: Syntax Errors using Packed Structures

How to preserve the order of input file?

Miranda Zhang

10/29/2010 02:56 pm

3

Added by Wilson Snyder over 1 year ago
RE: How to preserve the order of input file?

how to save a modified file?

Mike Z

08/15/2010 08:00 pm

6

Added by Mike Z almost 2 years ago
RE: how to save a modified file?

How to create new pin/port ?

Mike Z

08/16/2010 01:32 pm

2

Added by Mike Z almost 2 years ago
RE: How to create new pin/port ?

implicit wires ignored (bug 274)

max baker

07/31/2010 10:42 pm

0

Processing Unpacked Dimensions

Adam Jacobvitz

07/27/2010 07:46 pm

1

Added by Wilson Snyder almost 2 years ago
RE: Processing Unpacked Dimensions

Modiftying Attributes of Nets created using $module->new_net

Adam Jacobvitz

07/26/2010 11:31 pm

4

Added by Wilson Snyder almost 2 years ago
RE: Modiftying Attributes of Nets created using $module->...

How to access cell type?

Mike Z

07/12/2010 08:28 pm

1

Added by Wilson Snyder almost 2 years ago
RE: How to access cell type?

Is it possible to output all flip flop enable terms?

Shareef Jalloq

06/24/2010 09:16 am

1

Added by Wilson Snyder almost 2 years ago
RE: Is it possible to output all flip flop enable terms?

vppreproc cannot open file

Moti Litochevski

06/19/2010 10:12 pm

1

Added by Wilson Snyder almost 2 years ago
RE: vppreproc cannot open file

Bug in Verilog::Netlist with two-dimensional arrays.

Shareef Jalloq

05/20/2010 01:10 pm

1

Added by Shareef Jalloq about 2 years ago
RE: Bug in Verilog::Netlist with two-dimensional arrays.