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Issues

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	#	Tracker	Status	Priority	Subject	Assignee	Updated
	537	Issue	AskedReporter	Normal	Explicit hierarchical reference not resolving in Verilog::Net (CELL outside of module definition)		07/28/2012 11:22 pm
	527	Issue	AskedReporter	High	segmentation fault in Preproc.so	Wilson Snyder	07/15/2012 03:22 pm
	526	Issue	Feature	Normal	Support UVM	Wilson Snyder	06/21/2012 01:10 pm
	256	Issue	Assigned	Normal	vhier support of "myreg <= #`FFDLY 'b0;" Verilog notation	Wilson Snyder	05/07/2012 12:36 pm
	426	Issue	Feature	Normal	Add ability to not process some `ifdefs		12/23/2011 02:48 pm

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