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Verilog::Pli::Net

Verilog::Pli::Net - Verilog PLI tied net access hash

  use Verilog::Pli::Net;

  $NET{"hier.signal"} = 1;
  print "Signal now is ", $NET{"hier.signal"};
  foreach (keys %NET) { print "Found signal $_\n"; }
  (exists $NET{"bad"}) or die "Net 'bad' doesn't exist.";

  tie %PLINET, 'Verilog::Pli::Net', 'top.hier.submod.pli;
  print "top.hier.submod.pli.something = ", $PLINET{"something"}, "\n";

This package creates a tied hash %NET, that fetching from or storing to affects the Verilog signal named the same as the hash key. The hierarchy may be placed in front of the signal names using standard dot notation, or if not found, the scope from when the tie was established, or later scope() calls is prepended to the passed signal name.

Signal names may have a leading %b: %d: %x: or %s: to return or set the value in the binary, decimal, hex, or string format respectively. Values may have a leading 0b or 0x to set the value in binary or hex format respectively.

scope

Read or change the default scope used when a signal is not found with the name passed. Note you need to pass the class, use the tied function to convert from the tied hash to the class name.

The latest version is available from CPAN or http://www.veripool.com/.

Copyright 1998-2007 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.

Wilson Snyder <wsnyder@wsnyder.org>

Verilog::Pli

Verilog::Pli

Verilog::Pli - Verilog PLI routine calls

  use Verilog::Pli;

This package allows access to Verilog PLI routines from perl. See the Verilog PLI Reference Manual for more information on these functions.

This package has only been tested with VCS. It should work with other simulators, though different header files may need to be included.

mc_scan_plusargs (switch)

Return string if switch is set on command line.

Verilog::Pli::io_printf (format, arg1)

Print a string using Verilog I/O. Try to use Verilog::Pli::IO instead of this routine.

tf_dofinish

Finish the simulation.

tf_dostop

Stop the simulation.

tf_gettime

Return simulation time.

tf_igettime

Return simulation time for the passed instance.

tf_getinstance

Return the current instance.

Verilog::Pli::IO, Verilog::Pli::Net

Verilog::Pli::IO

Verilog::Pli::IO - Verilog PLI I/O rerouting

  use Verilog::Pli::IO;

  tie(*VOUT,'Verilog::Pli::IO');
  print VOUT "This will go to screen and any sim logs.\n";
  Verilog::Pli::IO->tie_stdout();
  print "As will this.\n";
  printf STDERR "And %s", "this.\n";

This package allows a file to be outputted through the Verilog PLI io_printf function, thus logging output on the screen as well as in any log files.

Verilog::Pli::IO::tie_stdout ()

Connect STDOUT and STDERR to use the PLI printing handles.

PRINT =item PRINTF

Standard handle methods.

Verilog::Pli