- Email: Must_Login
- Registered on: 08/27/2009
- Last connection: 04/10/2013
Reported issues: 2
- 06:44 pm Verilator Issue #634: Incorrect simulation in presence of MULTIDRIVEN
- Confirmed master branch passes my full design. Thanks Wilson.
- 02:08 am Verilator Issue #634: Incorrect simulation in presence of MULTIDRIVEN
- Either of these fixes allows my original design to simulate correctly now.
- 01:00 am Verilator Development: RE: Implementing SystemVerilog 'alias'
- I have a similar looking fragment with inout signals using port references supported in Verilog-2001....
- 07:31 pm Verilator Issue #634: Incorrect simulation in presence of MULTIDRIVEN
- Thanks for doing the digging into this. That certainly seems like a good place to work in a fix. I would be concerned...
- 10:28 pm Verilator Issue #634 (Closed): Incorrect simulation in presence of MULTIDRIVEN
- I'm noticing a complex issue with incorrect simulation result in my design. I've managed to reproduce in a simpler te...
- 01:41 am Verilator Issue #550: Memory corruption when parsing modules with triangle dependancy
- Thanks. My design now passes with latest git.
- 07:08 pm Verilator Issue #550 (Closed): Memory corruption when parsing modules with triangle dependancy
- There is memory corruption when modules are instantiated with a triangle pattern. The error only occurs if C is insta...
- Running Verilator-3.713 I notice that when a module isn't inlined (either by -Oi, or because it is large) that V3Loca...
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