Veripool

05/02/2013

06:44 pm Verilator Issue #634: Incorrect simulation in presence of MULTIDRIVEN

Confirmed master branch passes my full design. Thanks Wilson.

04/10/2013

02:08 am Verilator Issue #634: Incorrect simulation in presence of MULTIDRIVEN

Either of these fixes allows my original design to simulate correctly now.

01:00 am Verilator Development: RE: Implementing SystemVerilog 'alias'

I have a similar looking fragment with inout signals using port references supported in Verilog-2001....

04/09/2013

07:31 pm Verilator Issue #634: Incorrect simulation in presence of MULTIDRIVEN

Thanks for doing the digging into this. That certainly seems like a good place to work in a fix. I would be concerned...

03/18/2013

10:28 pm Verilator Issue #634 (Closed): Incorrect simulation in presence of MULTIDRIVEN

I'm noticing a complex issue with incorrect simulation result in my design. I've managed to reproduce in a simpler te...

08/16/2012

01:41 am Verilator Issue #550: Memory corruption when parsing modules with triangle dependancy

Thanks. My design now passes with latest git.

08/15/2012

07:08 pm Verilator Issue #550 (Closed): Memory corruption when parsing modules with triangle dependancy

There is memory corruption when modules are instantiated with a triangle pattern. The error only occurs if C is insta...

08/27/2009

07:01 pm Verilator Development: V3Localize not working outside of toplevel

Running Verilator-3.713 I notice that when a module isn't inlined (either by -Oi, or because it is large) that V3Loca...