Adolfo Sanchez
- Email: Must_Login
- Registered on: 10/07/2009
- Last connection: 11/14/2009
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11/14/2009
- I'm trying to do a verification enviroment for a managment unit of an MAC.
But I've problems becouse the Verilog Mod...
10/07/2009
- I was trying to make a VPI Interface with systemc usign Verilator.
The Verilog model is a simple 4-bits full adder.
...
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