Veripool

01/07/2010

12:28 am Verilator Usage: RE: Converting VCD file to LXT file during simulation

Another nice trick so that you don't have to type the "vcd2lxt2 ..." command multiple times:
( for (( ;; )); do ...

07/16/2009

04:26 pm Verilator Usage: Converting VCD file to LXT file during simulation

I found a way to convert the VCD file output by Verilator to an LXT2 file during the simulation. This substantially ...

05/12/2009

05:45 pm Verilator Issue #86 (Closed): Instructions for updating git download would be helpfull

It would be helpful for non-users of git to add the repository update command "git pull" to the Download link.

12/27/2008

04:55 am Verilator Issue #46 (Closed): signal not generated in state machine

The attached code demonstrates a problem with state machines using Verilator 3.681.<br/>
<br/>
After the strobe "my...

11/22/2008

04:58 am Verilator Issue #45 (Closed): clocks and signals not recognized in generate loops

The attached source illustrates two error messages associated with clocks and registers within generate statements:<b...

09/12/2008

10:30 am Verilator Usage: RE: Simulating Xilinx Projects

This attachment includes the file tb.cc missing in my original posting.

09/10/2008

01:31 pm Verilator Usage: Simulating Xilinx Projects

This is a summary of what I've learned to do to simulate Xilinx projects using Verilator. Using the techniques descr...

06/19/2008

01:39 pm Verilator Issue #14 (Closed): Verilator Doesn't catch duplicate declaration of signal

The attached Verilog file declares the signal "clk" twice, once as an input and once in the body, but no error messag...