Veripool

11/24/2009

06:50 pm Verilog-Perl Issue #192 (Closed): SV unrecognized covergroup

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11/16/2009

10:48 pm Verilog-Perl Issue #189 (Closed): SV unrecognised syntax #4

10:06 pm Verilog-Perl Issue #188 (Rejected): SV unrecognised syntax: 2D params/typedef instantiations

Fails for me. Strange, thought bug183 would've fixed this.

09:58 pm Verilog-Perl Issue #187 (Closed): SV unrecognised syntax #2

09:08 pm Verilog-Perl Issue #186 (Rejected): (Allegedly) more SV unrecognised syntax

Please see the attached files! Please excuse if multiple files fail for the same root cause - I tried hard to uniquif...

11/12/2009

08:08 pm Verilog-Perl Issue #183: SV unrecognized syntax: Multidimensioned typedef references

Oops! I didn't know it will smear the new lines :( Attaching the file

08:06 pm Verilog-Perl Issue #183 (Closed): SV unrecognized syntax: Multidimensioned typedef references

%Error: test1.v:30: syntax error, unexpected '[', expecting IDENTIFIER or '='...