Veripool

07/08/2011

04:30 pm Verilator Development: RE: Bidirectional arrayed ports

Chandan,
While it is in the plans to support bidirectional arrayed ports, it is not currently scheduled. Sorry.

03/24/2010

07:36 pm Verilator Patch #226: Improve error handling on slices of packed arrays

I did a little more digging into this problem, and it seems like a false alarm. I checked out the main branch without...

08:46 am Verilator Patch #226: Improve error handling on slices of packed arrays

Previously I mentioned that even after reverting this patch that I was still having problems. That was not correct. S...

07/02/2009

05:21 am SystemPerl Issue #100 (Closed): uint32_t undefined in SpCommon.h

I am using the new verilator and system perl v1.321 rpms for Fedora and ran into the following error when compiling w...

05/08/2009

05:44 pm Verilator Usage: Specifying verilator options externally

I have a synthesized netlist. Is there a way, other than through inline verilog comments, to set options such as 'pu...

05/02/2009

06:22 pm Verilog-mode Issue #82 (Closed): Comma Incorrectly Deletes

Auto mode incorrectly deletes the comma after the a in the following verilog code:...

01/30/2009

05:33 pm Verilator Issue #63 (Feature): False Signal unoptimizable: circular logic warning

See attached test case showing the problem. This example shows how bit 0 of a bus is used to generate bit 1 of the s...

01/26/2009

04:59 pm Verilator Issue #58: Use of // verilator public with inout causes error

Jeremy,
I recently added very limited support for tristates to verilator, and it is currently *very* fragile. The o...

01/23/2009

09:05 pm Verilator Issue #56 (Assigned): Inout signals within modules don't propogate correctly.

01/22/2009

08:39 pm Verilator Issue #55 (Closed): Tristate: Tracing an inout signal is broken

Conventionally when you trace a tristate signal the driven signal propagates up and down the hierarchy to all modules...