Veripool

01/31/2011

08:20 am Verilator Issue #323 (Closed): Coding error results in internal error

Hello, I triggered an internal error with a bug in my registerfile generator.<br>
So again I did not use AUTOINST ;-...

01/29/2011

06:04 pm Verilator Issue #321 (Closed): lint does not complain about double port usage

Hello,
we found a pretty simple problem in the linter, when people are not using other tools to stumble upon such ...

01/03/2011

12:13 am Verilator Usage: RE: correct clocking/interfacing

Thanks you for your quick answer, with that information I tracked down the problem, the C++ interface was faster than...

01/02/2011

12:31 am Verilator Usage: correct clocking/interfacing

Hello,
I want to simulate some middle sized design (as in the generated .cpp files are 120 MB in size), that has a...

12/20/2009

12:14 am Verilator Usage: Using a verilated module multiple times

Hello,
i would like to use the same verilated design multiple times in a network simulation.
Just to be sure.
Wi...