Veripool

05/02/2012

01:17 am Verilog-Perl Issue #504 (NoFixNeeded): Vrename aborts when parsing a large netlist

I've a 520MByte Verilog netlist that I'm trying to load using "Vrename --list --xref netlist.v" command.
My system...

06/08/2010

08:55 pm Verilog-Perl Issue #262 (Closed): Add support for complex ports in Verilog-Perl

The following port declaration causes an error: "unexpected '{'. expecting CLASS-IDENTIFIER..."
module my_module (...

05/27/2010

05:44 pm Verilog-Perl Issue #256 (Assigned): vhier support of "myreg <= #`FFDLY 'b0;" Verilog notation

When running vhier on the code with "myreg <= #`FFDLY 'b0;" Verilog notation, I'm getting the following error:

...

03/02/2010

06:44 pm Verilog-Perl Using: Removing duplicated ports in the module definition

Some netlisting tools create modules with duplicated ports and overlapping ranges, as in the following example:
...