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Wilson Snyder
- Email:
- Registered on: 03/14/2008
- Last connection: 03/11/2010
Projects
- BugVise (Manager, 04/02/2008)
- CovVise (Manager, 10/01/2008)
- Dinotrace (Manager, 04/02/2008)
- Gspice (Manager, 04/02/2008)
- IPC::Locker (Manager, 04/02/2008)
- Schedule::Load (Manager, 04/02/2008)
- SVN::S4 (Manager, 04/02/2008)
- Synopsys-Modes (Manager, 04/02/2008)
- SystemPerl (Manager, 04/02/2008)
- TestProject (Manager, 04/02/2008)
- Verilator (Manager, 03/16/2008)
- Verilog-mode (Manager, 04/02/2008)
- Verilog-Perl (Manager, 04/02/2008)
- Verilog-Pli (Manager, 04/02/2008)
- Veripool (Manager, 03/16/2008)
- Voneline (Manager, 04/02/2008)
- Vregs (Manager, 04/02/2008)
Activity
Reported issues: 33
Today
- 12:37 pm Verilog-Perl Issue #222 (Resolved): An example in Verilog::EditFiles doesn't work
- Fixed in git for next release, 3.232
- 12:33 pm Verilog-Perl Issue #222 (Resolved): An example in Verilog::EditFiles doesn't work
- Bug via RT
Thu Mar 11 01:45:25 2010: Request 55460 was acted upon.
Transaction: Ticket created by OutputLogic
...
03/10/2010
- 02:03 pm Verilator Issue #220: Latch issue with clock gating signal
- There's two problems with the test you sent; first it relies on time zero behavior, it's better to make the same crc/...
03/05/2010
- 04:03 pm Verilog-mode Wiki edit: Intro (#19)
- 03:35 pm Verilog-Pli Wiki edit: Intro (#13)
- 03:34 pm SystemPerl Wiki edit: Intro (#9)
- 03:34 pm Synopsys-Modes Wiki edit: Intro (#6)
- 03:34 pm Schedule::Load Wiki edit: Intro (#8)
- 03:33 pm Gspice Wiki edit: Intro (#5)
- 03:33 pm CovVise Wiki edit: Intro (#11)
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