Wilson Snyder
- Email: Must_Login
- Registered on: 03/14/2008
- Last connection: 02/04/2012
Projects
- BugVise (Manager, 04/02/2008)
- CovVise (Manager, 10/01/2008)
- Dinotrace (Manager, 04/02/2008)
- Force-Gate-Sim (Manager, 09/22/2010)
- Gspice (Manager, 04/02/2008)
- IPC::Locker (Manager, 04/02/2008)
- Metrigator (Manager, 06/07/2010)
- Rsvn (Manager, 08/18/2010)
- Schedule::Load (Manager, 04/02/2008)
- SVN::S4 (Manager, 04/02/2008)
- Synopsys-Modes (Manager, 04/02/2008)
- SystemPerl (Manager, 04/02/2008)
- TestProject (Manager, 04/02/2008)
- Verilator (Manager, 03/16/2008)
- Verilog-mode (Manager, 04/02/2008)
- Verilog-Perl (Manager, 04/02/2008)
- Verilog-Pli (Manager, 04/02/2008)
- Veripool (Manager, 03/16/2008)
- Voneline (Manager, 04/02/2008)
- Vregs (Manager, 04/02/2008)
Activity
Reported issues: 42
Today
- 02:35 am Verilog-mode Issue #386: Indenting of user-defined data types
- BTW verilog-typedef-regexp if used needs to be specified as "\\w+_s\\>" or similar, since it needs to match in the mi...
- 02:32 am Verilog-mode Issue #386: Indenting of user-defined data types
- I searched for "int" in verilog-mode.el and followed verilog-declaration-core-re to verilog-declaration-re. Adding t...
- 01:54 am Verilog-mode General: RE: add type keywords?
- Putting notes in the bug.
- 01:42 am Verilog-mode General: RE: control module port list indentation?
- Sorry, I've happily left the indent stuff to Mac. You'll need to poke around to find it.
Perhaps I'm missing some... - 12:10 am Verilator Issue #304 (Closed): What can cause: Internal Error: Non-cutable edge forms a loop
- This issue was resolved with a workaround.
02/04/2012
- 09:51 pm Verilog-mode Using AUTOs: RE: Allowing auto-output to propagate up even though it's used internally
- Sorry, but there isn't a way to do this now. The intent is that if you have a signal like that, then you should simp...
02/03/2012
- 11:40 pm Verilog-mode General: RE: control module port list indentation?
- I don't think there's a setting for that, but I don't know for sure.
02/02/2012
- 08:46 pm Verilog-mode Issue #435: Indenting comments on declarations in v736
- There's really two things here.
The first is the space between "input" and the signal name. This was changed in r...
01/31/2012
- 01:13 pm Verilator Usage: RE: Verilator Parser (bison) as standalone parser for SystemVerilog files?
- It's written in C++, so in theory yes, but there's no API, you'd have to dig in and make one yourself.
01/30/2012
- 01:31 pm SystemPerl General: RE: Debian packages for SystemPerl and SystemC 2.3.0
- Hmm, yes I think /usr/include/systemperl is better. I'll add some prints to the installation process as you suggest.
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