Wilson Snyder

BugVise (Manager, 04/02/2008)
CovVise (Manager, 10/01/2008)
Dinotrace (Manager, 04/02/2008)
Force-Gate-Sim (Manager, 09/22/2010)
Gspice (Manager, 04/02/2008)
IPC::Locker (Manager, 04/02/2008)
Metrigator (Manager, 06/07/2010)
Rsvn (Manager, 08/18/2010)
Schedule::Load (Manager, 04/02/2008)
SVN::S4 (Manager, 04/02/2008)
Synopsys-Modes (Manager, 04/02/2008)
SystemPerl (Manager, 04/02/2008)
TestProject (Manager, 04/02/2008)
Verilator (Manager, 03/16/2008)
Verilog-mode (Manager, 04/02/2008)
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Verilog-Pli (Manager, 04/02/2008)
Veripool (Manager, 03/16/2008)
Voneline (Manager, 04/02/2008)
Vregs (Manager, 04/02/2008)

Reported issues: 46

11:08 am Verilator Issue #652 (Assigned): Width mismatch problem: '0 is unsized, and IEEE says clearly 'Unsized constant numbers shall not be used in concatenations." I will fix the ...
02:25 am Verilog-mode Using AUTOs: RE: Using verilog-auto-inst-param-value: Looks generally correct.
Is ADDR_WIDTH in a #() as described in [[Verilog-mode-Help#verilog-auto-inst-param-value]...
12:20 am Verilator Issue #651 (Resolved): Different versions of GCC cause Verilator generated models to succeed or fail: Thanks for the patch, makes sense.
Fixed in git towards 3.848.
12:09 am Verilator Issue #650 (Closed): "make test" runs out of processes: Fixed it to not use tee at all.
Fixed in git towards 3.848.

02:46 am Verilator Usage: RE: using split VCD trace: Thanks for the pointer. BTW would be neat to see the Amiga work too; spent a lot of time on an Amiga 1000 long ago w...
02:41 am Verilator Issue #648 (Assigned): Error-BLKANDNBLK with nested modules in generate block: I'm not immediately sure how to fix this. The conflict is at that port since a single bit is selected that is effect...
02:14 am Verilator Development: RE: Matching AST patterns: That's basically how the V3Const stuff works. It hasn't been made general purpose though. While that's doable, unle...
02:11 am Verilog-mode Issue #562: bus width alignment: BTW to find the logic around this in the sources, look for verilog-auto-lineup. I would suggest adding an additional...
12:31 am Verilator Issue #649 (Feature): support for streaming operators: I don't personally have a huge interest in this as it's uncommon syntax, but if you or someone else would like to tak...

11:52 pm Verilator Issue #645 (Resolved): VL_INW and VL_OUTW macros require 4 arguments, but only 3 given

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