Veripool

04/15/2010

12:28 pm Verilog-Perl General: RE: Reg: generate - endgenerate constructs.

I agree with you. While I am trying to get the hierarchical path of particular Flip-Flop the hierarchical path is inc...

12:27 pm Verilog-Perl General: RE: Reg: generate - endgenerate constructs.

Hi,
I agree with you. While I am trying to get the hierarchical path of particular Flip-Flop the hierarchical ...

11:58 am Verilog-Perl General: Reg: generate - endgenerate constructs.

Hi,
This Verilog Parser will it support the generate-endgenerate constructs?
Thanks & Regards,
Prabh...

04/14/2010

01:20 pm Verilog-Perl General: Reg: Find Hierarchical path

Hi,
In my design I need to find the hierarchical path of particular Flip-Flop. For this any function availa...

09:31 am Verilog-Perl General: Reg: *.vh

This package ( Verilog::Parser ) can parse the vhdl source file?
Regards,
Prabhu